DC-DC Converter Design and Magnetics--Calculating the “Other” Worst-case Stresses

Having validated our choice of inductor, we can look a little more closely at the important issue of how the wide-input range impacts the other key parameters and stresses in our proposed converter. This also helps in correctly selecting the other power components.

Worst-case Core Loss

In the above so-called "general inductor design procedure," we have actually been working at VINMAX for a buck, and at VINMIN for a boost or buck-boost. The reason was that the inductor sees the highest peak current, at this voltage end, so we have to "insure" the magnetics design at this particular point. But this point may not be the worst-case point for the other stresses in the power supply, and we need to start understanding that clearly now.

Let us first focus on the inductor itself. The point at which we are doing the inductor design will usually always give us the worst-case temperature rise too. But that is because the IDC component of the inductor current is the dominant term. If for any reason, we are interested in knowing what the maximum core loss component of the total loss is, we should realize, looking back at Fgr. 4, that though the dc level may be going up, the ac component (on which the core loss term depends) may be decreasing (or even having an odd-shaped profile, as for the boost).

From Fgr. 4, we see that IAC increases at high input voltages for both the buck and the buck-boost. For a buck, the general inductor design calculation above was carried out at VINMAX and that just happens to be the point at which the core loss is a maximum too.

Therefore, calculating the core loss at VINMAX as we did in the previous example does coincidentally also give us the worst-case core loss.

However, if we were doing the calculation for a buck-boost, our general inductor design calculation would be being carried out at VINMIN. But the core loss is a maximum at VINMAX. Similarly, for a boost, we would also be carrying out the general inductor design calculation at VINMIN. But the worst-case core loss for this topology occurs at D = 0.5 (see IAC curve for boost in Fgr. 4). From the duty cycle equation of the boost, D = 0.5 corresponds to an input voltage equal to half the output.

Note: If for the boost, the input range of the given application does not include the D = 0.5 point, we need to identify which voltage end of the range provides a duty cycle closest to D = 0.5. And we need to then do the worst-case core loss calculation at that end (if so desired).

Generally, the core loss term, being such a small component of the total loss, is of no great concern to us, so we won't even bother to do a numerical calculation here. But the general procedure to handle such cases will become apparent as we study the other worst-case loss terms of the converter below.

But first let us now start annotating (or subscripting) some of the terms derived so far, just for gaining clarity in the discussion to follow. We should be clear that:

++ For a buck: The general inductor design procedure was carried out at VINMAX, that is, DMIN. So For example, the r we have set to 0.3-0.4 (and possibly re-calculated with the selected inductor) is actually 'rDMIN' to be precise. Similarly, the voltseconds, Et, we have calculated so far is actually 'EtDMIN.'

++ For a boost and buck-boost: If a similar general inductor design procedure were carried for these topologies, it would be done at VINMIN, that is, DMAX. So For example, the r we would have set to 0.3-0.4 (and possibly re-calculated with the selected inductor) would actually be 'rDMAX.' Similarly, the voltseconds, Et, we would have calculated so far is actually 'EtDMAX.' We need to keep these distinctions in mind, otherwise the following discussion can become confusing to no end!

Worst-case Diode Dissipation:

The general equation for the average diode current is

ID = IL × (1 - D) (any topology)

or equivalently

ID = IO × (1 - D) (buck)

ID = IO (boost and buck-boost)

This leads to a diode dissipation of (buck)

PD = VD × ID = VD × IO (boost and buck-boost)

For the buck, as the input voltage is raised, the duty cycle falls, and because the average inductor current IL remains fixed at IO, the average diode current increases. That means we get the worst-case diode current (and dissipation) at VINMAX for a buck. So we can just use the numbers we already have derived from carrying out the general inductor design procedure (at VINMAX).

For the boost and the buck-boost, as the input is raised, D decreases, but the average inductor current also falls, thereby keeping ID always fixed at IO. (We should remember that the boost and the buck-boost are unique in the sense that all the output current must pass through the diode when it conducts, so ID must necessarily be equal to IO at all times). That means the diode dissipation is independent of input voltage for these topologies. So we can, if we want, just use the numbers we already have derived from carrying out the general inductor design procedure (at VINMIN).

Finally, for the ongoing buck converter design example, the calculation is as follows:

Note that the general diode selection procedure is as follows:

The rule-of-thumb is to pick a diode with a current rating at least equal to, but preferably at least twice the worst-case average diode current given below (for low losses, since the diode forward drop decreases substantially if its current rating is increased):

++ For a buck- maximum diode current is IO x (1 - DMIN).

++ For a boost - maximum diode current is IO.

++ For a buck-boost - maximum diode current is IO.

Its voltage rating is usually picked to be at least 20% higher (~ "80% derating" - i.e. safety margin) than the worst-case diode voltage given below:

++ For a buck- maximum diode voltage is VINMAX.

++ For a boost - maximum diode voltage is VO.

++ For a buck-boost - maximum diode voltage is VO + VINMAX.

Worst-case Switch Dissipation:

For all topologies the average input current (and therefore switch current) must increase as the input voltage decreases, so as to continue to satisfy the basic power requirement expressed by PIN = IIN × VIN = PO/? (where ? is the efficiency, assumed fixed). Therefore, the switch RMS current is a maximum at VINMIN (i.e. DMAX) for all topologies.

For the boost and buck-boost, the general inductor design procedure is at DMAX in any case.

So we can directly use the numbers derived from that, to find the switch RMS current using the equation below: (any topology) where ILDMAX and rDMAX are, respectively, the average inductor current and current ripple ratio at DMAX (i.e. at VINMIN). DMAX can be calculated using ....

For the buck, the general inductor design procedure is at DMIN. So we cannot directly use the numbers derived from that to find the switch RMS current (by the previously given equation). We need to calculate rDMAX, but we only know rDMIN so far. Let us proceed with the required steps.

Note that the general switch selection procedure is as follows:

The rule-of-thumb is to pick a switch with a current rating at least equal to, but preferably at least twice the worst-case RMS switch current calculated above (for low losses, since the switch forward drop will decrease substantially if its current rating is increased) Its voltage rating is usually picked to be at least 20% higher (~ "80% derating" - i.e. safety margin) than the worst-case switch voltage given below

++ For a buck - maximum switch voltage is VINMAX.

++ For a boost - maximum switch voltage is VO.

++ For a buck-boost - maximum switch voltage is VO + VINMAX.

Worst-case Output Capacitor Dissipation:

Coincidentally, the worst-case output capacitor RMS current for all three topologies occurs at the same point at which the general inductor design procedure for each of them is carried out.

In other words, this point is VINMAX for the buck, and VINMIN for the boost and buck-boost.

So we should have no trouble, directly using the numbers derived from the general inductor design procedure, to find the worst-case RMS current of the output capacitor, using the equations below.

For the buck, we get:

So for example, if the ESR of the output capacitor is 10 Ohm, we get the dissipation: (any topology)

For the boost and the buck-boost, we need to use (boost and buck-boost)

Note that the general output capacitor selection procedure is as follows:

The rule-of-thumb is to pick an output capacitor with a ripple current rating equal to or greater than the worst-case RMS capacitor current calculated above. Its voltage rating is usually picked to be at least 20 to 50% higher than what it will see in the application (i.e. VO for all topologies). The output voltage ripple of the converter is also usually a concern. The total peak to peak output voltage ripple produced by the output capacitor is equal to its ESR multiplied by the worst-case peak to peak output current given below (ignoring the ESL of the capacitor):

++ For a buck - peak to peak capacitor current is IO × rDMIN. This is the same point at which the general inductor design procedure would have been carried out, and so rDMIN is already known.

++ For a boost - peak to peak capacitor current is IO × (1 + rDMAX/2)/(1 - DMAX).

This is the same point at which the general inductor design procedure would have been carried out for this topology, so rDMAX and DMAX are already known.

++ For a buck-boost - peak to peak capacitor current is IO × (1 + rDMAX/2)/ (1 - DMAX). This is the same point at which the general inductor design procedure would have been carried out for this topology, so rDMAX and DMAX are already known.

Worst-case Input Capacitor Dissipation:

For the buck-boost, things are much simpler, since the worst-case input capacitor RMS current occurs at DMAX, which is also the point at which we carry out the general inductor design procedure. So all the numbers available from that procedure can be used directly in the equation below (buck-boost)

For the buck and the boost, the worst-case input RMS capacitor current occurs at D = 0.5.

So we have to calculate 'r50,' that is, the current ripple ratio at D = 50% (or whatever voltage within the specified input range of our application range is closest to this point).

Let us do the numerical calculation for the buck, and the procedure will become clearer.

The input voltage at which D = 50% occurs for the buck is...

We see that our input range does not include this point. But the closest to it’s VINMAX.

However, coincidentally, this is already the point at which the general inductor design procedure was carried out. So we can use all the numbers derived from that procedure to calculate the input capacitor RMS current, using the equation below (buck):

So finally:

Note: If for our worked buck example, the input range was not 18-24 V but say 30-45 V, then the general inductor design procedure would clearly be carried out at 45 V. However, the input capacitor current would be a maximum at 30 V. So we can use the above equation for the RMS current, but we would now need to use rDMIN and DMAX. Therefore, knowing only rDMAX so far, we would need to calculate rDMIN by the same procedure presented earlier - that is, by recalculating the voltseconds, and so on.

Note that the general input capacitor selection procedure is as follows:

The rule-of-thumb is to pick an output capacitor with a ripple current rating equal to or greater than the worst-case RMS capacitor current calculated above. Its voltage rating is usually picked to be at least 20 to 50% higher than what it will see in the application (i.e. VIN_MAX for all topologies). The input voltage ripple of the converter is also usually a concern because a small part of it does get transmitted to the output. There can also be EMI considerations involved. In addition, every control IC has a certain (usually unspecified) amount of input noise and ripple rejection, and it may misbehave if the ripple is too much.

Typically, the input ripple needs to be kept down to less than ±5% to ±10% of the input voltage. The total peak to peak input voltage ripple produced by the input capacitor is equal to its ESR multiplied by the worst-case peak to peak input current given below (ignoring the ESL of the capacitor):

++ For a buck - peak to peak capacitor current is IO × (1 + rDMIN/2). This is the same point at which the general inductor design procedure would have been carried out, and so rDMIN is already known.

++ For a buck-boost - peak to peak capacitor current is IO × (1 + rDMAX/2)/ (1 - DMAX). This is the same point at which the general inductor design procedure would have been carried out for this topology, so rDMAX and DMAX are already known.

++ For a boost - peak to peak capacitor current at the worst-case point for this parameter (i.e. D = 0.5) is equal to 2 × IO × r50 where...

Note that if the input range does not include the D = 0.5 point, we need to look for the input voltage end closest to D = 0.5. Then we can use the general equation for the peak to peak input capacitor current...where r and D correspond to this particular worst-case input voltage end. To find r we can use...where L is in H, and f is in Hz.

That completes the converter and magnetics design procedure. Next we will move on to off-line converters.