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7. D/A Converters
Digital-to-analog conversion is an essential function in data processing systems. D/A converters provide an interface between the digital output of signal processes and the analog world. Moreover, as discussed previously, multistep ADCs employ interstage DACs to reconstruct analog estimates of the input signal.
Each of these applications imposes certain speed, precision, and power dissipation requirements on the DAC, mandating a good understanding of various D/A conversion techniques and their trade-offs.
7.1 General Considerations
A digital-to-analog converter produces an analog output, A, proportional to the digital input D: A = to D
… where alpha is a proportionality factor. Since D is a dimensionless quantity, alpha sets both the dimension and the full-scale range of A. For example, if alpha is a current quantity, I_REF, then the output can be expressed as
A =I_REF x D
In some cases, it’s more practical to normalize D with respect to its full-scale value, 2^m, where m is the resolution. For example, if c~ is a voltage quantity, VREF,
A = V_REF D/2^m
From (eq 7) and (eq 8), we can see that, in a D/A converter, each code at the digital input generates a certain multiple or fraction of a reference at the analog output. In practical monolithic DACs, conversion can be viewed as a reference multiplication or division function, where the reference may be one of the three electrical quantities: voltage, current, or charge.
The accuracy of this function determines the linearity of the DAC, while the speed at which each multiple or fraction of the reference can be selected and established at the output gives the conversion rate of the DAC. FIG. 46 shows the input/output characteristic of an ideal 3-bit D/A converter. The analog levels generated at the output follow a straight line passed through the origin and the full-scale point.
FIG. 46 Input/output characteristic of an ideal 3-bit DAC
We should mention that, in some applications such as "companding" (compressing and expanding) DACs, the desired relationship between D and A is nonlinear , but in this section we discuss only "linear" or "uniform" DACs; that is, those that ideally behave according to equation (7) or (8). The digital input to a DAC can assume any predefined format but eventually must be of a form easily convertible to analog. Table 4 shows three formats often used in DACs: binary, thermometer, and one-of-n codes. The latter two are shown in column form to make visualization easier.
7.2 Performance Parameters and Data Sheet Terminology
In manufacturers, data books, many terms are used to characterize DACs.
The following is a basic guideline only, and the reader is referred to manufacturers, data sheet guidelines for a more application-oriented description.
FIG. 47 illustrates some of these metrics that are listed in Table 5.
Among these parameters, DNL and INL usually are determined by the accuracy of reference multiplication or division, settling time and delay are functions of output loading and switching speed, and glitch impulse depends on the D/A converter architecture and design.
TABLE 4 Binary, Thermometer, and One-of-n Codes
7.3 Voltage Division
A given reference voltage, VREF, can be divided into N equal segments using a ladder composed of N identical resistors R1 = R2 .... --RN (N typically is a power of 2; FIG. 48(a)). An m-bit DAC requires a ladder with 2 m resistors, manifesting the exponential growth of the number of resistors as a function of resolution.
An important aspect of resistor ladders is the differential and integral nonlinearity they introduce when used in D/A converters. These errors result from mismatches in the resistors composing the ladder.
The DACs most commonly used as examples of simple DAC structures are binary weighted DACs or ladder networks, but although simple in structure, these require quite complex analysis. The simplest structure of all is the Kelvin divider shown in FIG. 48(b). An N-bit version of this DAC simply consists of 2 N equal resistors in series. The output is taken from the appropriate tap by closing one of the 2 N switches.
FIG. 47 Parameters of DACs: (a) Static parameters, (b) Dynamic parameters
7.4 Current Division
Instead of using voltage division, current division techniques can be used in DACs. FIG. 49(a) shows how a reference current IREF can be divided into N equal currents using N identical (bipolar or MOS) transistors. These currents can be combined to provide binary weighting as depicted in FIG. 49(b), using a 3-bit case as the example. In this simple implementation, an m-bit DAC requires 2 m-1 transistors, resulting in a large number of devices for m > 7.
While conceptually simple, the implementation of FIG. 49(a) has two drawbacks: the stack of current division transistors on top of I_REF limits output voltage range, and IREF must be N times each of the output currents. This requires a high-current device for the I_REF source transistor. There are techniques for alleviating these problems. DACs that employ current division suffer from three sources of nonlinearity" current source mismatch, finite output impedance of current sources, and voltage dependence of the load resistor that converts the output current to voltage.
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TABLE 5 DAC Performance Parameters Parameter Description
Differential nonlinearity (DNL) Integral nonlinearity (INL) Offset Gain error Settling time Glitch impulse area Latency Signal-to-noise (+ distortion) ratio (SNDR or SINAD)
Maximum deviation in the output step size from the ideal value of one least significant bit (LSB) Maximum deviation of the input/output characteristic from a straight line passed through its end points. The difference between the ideal and actual characteristics is called the INL profile.
Vertical intercept of the straight line passed through the end points.
Deviation of the slope of the line passed through the end points from its ideal value (usually unity). Time required for the output to experience a full-scale transition and settle within a specified error band around its final value.
Maximum area under any extraneous glitch that appears at the output after the input code changes, also called glitch energy in the literature, even though it has no energy dimension.
Total delay from the time the digital input changes to the time the analog output has settled within a specified error band around its final value. Latency may include multiples of the clock period if the digital logic in the DAC is in a pipeline.
Ratio of the signal power to the total noise and harmonic distortion at the output when the input is a (digital) sinusoid.
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7.5 Charge Division
A reference charge, QREF, can be divided into N equal packets using N identical capacitors con figured as in FIG. 50. In this circuit, before S1 turns on, C1 has a charge equal to QREF, while C2 ..... CN have no charge. When S1 turns on, QREF is distributed equally among C1 ..... CN yielding a charge of QREF/N on each. Further subdivision can be accomplished by disconnecting one of the capacitors from the array and redistributing its charge among some other capacitors.
While the circuit of FIG. 50 can operate as a D/A converter if a separate array is employed for each bit of the digital input, the resulting complexity prohibits its use for resolutions above 6 bits. A modified version of this circuit is shown in FIG. 51(a). Here, identical capacitors C1 ..... C N = C share the same top plate, and their bottom plates can be switched from ground to a reference voltage, VREF, according to the input thermometer code. In other words, each capacitor can inject a charge equal to CVREF onto the output node, producing an output voltage proportional to the height of the thermometer code.
FIG. 48 DAC using a voltage division technique: (a) Basic resistor ladder,
(b) Kelvin divider (3-bit DAC example)
FIG. 49 Current division (a) Uniform division, (b) Binary division
FIG. 50 Simple charge division
FIG. 51 Modified charge division: (a) Configuration, (b)Circuit of (a)
in discharge mode, (c) Circuit of (a) in evaluate mode
The circuit operates as follows. First, Sp is on and the bottom plates of C1 ..... CN are grounded, discharging the array to 0 ( FIG. 51(b)). Next, Sp turns off, and a thermometer code with height j is applied at D] ..... DN, connecting the bottom plate of C1 ..... Cj to VREF and generating an output equal to jVREF/N ( FIG. 51 (c)). This circuit, in a strict sense, is a voltage divider rather than a charge divider. In fact, the expression relating its output voltage to VREF and the value of the capacitors is quite similar to that of resistor ladders. Nonetheless, in considering nonlinearity and loading effects, it’s helpful to remember that the circuit's operation is based on charge injection and redistribution.
The nonlinearity of capacitor DACs arises from three sources: capacitor mismatch, capacitor nonlinearity, and the nonlinearity of the junction capacitance of any switches connected to the output code. For details and implementation of capacitor DACs.
7.6 DAC Architectures
With the basic principles of D/A conversion explained, we can study this function from architectural perspective. This section describes D/A converter architecture based on resistor ladders and current steering arrays, with an emphasis on stand-alone applications. While capacitor DACs frequently are used in ADCs, they have not been popular as stand-alone circuits.
7.6.1 Resistor Ladder DAC Architectures
The simplicity of resistor ladder DACs using MOS switches makes these architectures attractive for many applications. Simple ladder networks with simple voltage division as per Section 7.3 have several drawbacks: they require a large number of resistors and switches (2 m, where m is the resolution) and exhibit a long delay at the output. Consequently, alternative ladder topologies have been devised to improve the speed and resolution.
7.6.1.1 Ladder Architecture with Switched Subdividers
In high-resolution applications, the number of devices in a DAC can be prohibitively large. It therefore is plausible to decompose the converter into a coarse section and a fine section so that the number of devices become proportional to approximately 2m/2 rather than 2 m, where m is the overall resolution.
Such an architecture is shown in FIG. 52(a). In this circuit, a primary ladder divides the main reference voltage, generating 2 j equal voltage segments. One of these segments is selected by the j most significant bits of (k + j)= m. If k = j, the number of devices in this architecture is proportional to 2m/2. It also is possible to utilize more than two ladders to further reduce the number of devices at high resolutions.
FIG. 52(b) depicts a simple implementation of this architecture using MOS switches that are driven by one-of-n codes in both stages. Depending on the environment, these codes are generated from binary or thermometer code inputs. The details and drawbacks of this implementation are discussed below.
FIG. 52 Resistor ladder DAC with a switched subdivider: (a) Block diagram,
(b) Implementation
7.6.1.2 Intermeshed Ladder Architecture
Some of the drawbacks of ladder DACs can be alleviated through the use of intermeshed ladder architectures. In these architectures, a primary ladder divides the main reference voltage into equal segments, each of which is subdivided by a separate, fixed secondary ladder. FIG. 53 illustrates such an arrangement (Analog Devices, 1996), where all the switches are controlled by a one-of-n code.
The intermeshed ladder has several advantages over single-ladder or switched-ladder architectures. This configuration can have smaller equivalent resistance at each tap than a single-ladder DAC having the same resolution, allowing faster recovery. Also, since the secondary ladders don’t switch, their loading on the primary ladder is constant and uniform. Furthermore, the DNL resulting from finite on-resistance of switches does not exist here.
FIG. 53 Intermeshed resistor ladder DAC with one-level multiplexing
7.6.2 Current Steering Architecture
Most high-speed D/A converters are based on a current steering architecture.
Since these architectures can drive resistive loads directly, they require no high-speed amplifiers at the output and potentially are faster than other types of DACs.
While the high-speed switching of bipolar transistors makes them the natural choice for current-steering DACs, many designs have been recently reported in CMOS technology as well.
7.6.2.1 R-2R Network-Based Architectures
To realize binary weighting in a current steering DAC, an R-2R ladder can be incorporated to relax device scaling requirements. FIG. 54(a) illustrates an architecture that employs an R-2R ladder in the emitter network. A network with an R-2R ladder in collector networks is shown in FIG. 54(b).
7.6.3 Other Architectures
Other architectures for DACs include segmented current steering versions, multiplying DACs, and Z-A types.
FIG. 54 Current steering DAC with an R-2R ladder: (a) R-2R ladder in the emitter, (b) R-2R ladder in the collector
8 Data Acquisition System Interfaces
8.1 Signal Source and Acquisition Time
Continued demand for lower-power, lower-cost systems increases the likelihood that a mixed-signal design will operate from a single 3.3 or 5 V power supply. Doing away with traditional 4-15 V analog power supplies can help you to meet your power and cost goals, but it also will eliminate some of your options.
Most low-voltage ADC and data acquisition system chips are designed for easy analog and digital interfaces. The ICs' digital interfaces generally are compatible with popular microcontrollers, and the devices almost always can accept analog input signals that range from ground to the positive supply voltage; the span is set by an internal or external bandgap voltage reference. Virtually all ADCs that operate from 5 V or less are CMOS devices that use arrays of switches and capacitors to perform their conversions. Although the architectural details vary from design to design, the input stage of this type of converter usually includes a switch and a capacitor that present a transient load to the input signal source. The simplified schematic of FIG. 55 shows how these input stages affect the circuits that drive them.
FIG. 55 Simplified interface between a low-voltage ADC and a signal source
FIG. 56 The effect of source resistance: (a) Insufficient acquisition
time, (b) Slowing the clock to increase acquisition time
RON is not a separate component; it’s the on-resistance of the internal analog switch. Sampling capacitor C s connects to an internal bias voltage, whose value depends on the ADC's architecture. In a sampling ADC, the switch closes once per conversion, during the acquisition (sampling) time. The on-resistance of the sampling switches ranges from about 5 to 10 kf2 in many low-resolution successive-approximation ADCs to 70 f2 in some multistep or half-flash converters.
The capacitors can be as small as 10 pF in lower-resolution successive-approximation converters and 100 pF or more in higher-resolution devices.
When the sampling switch closes, the capacitor begins to charge through the switch and source resistance. After a time interval that usually is controlled by counters or timers within the ADC, the switch opens and the capacitor stops charging. The acquisition time described in FIG. 10(c) is actually the time during which the switch is closed and the capacitor charges. As long as the source impedance is low enough, the capacitor has time to charge fully during the sampling period and no conversion errors occur. Most input stages are conservatively designed and can work properly at their rated speeds with a reasonable source resistance (1 kf2 is common). Larger source impedance slows the charging of the sampling capacitor and can cause significant errors unless you take steps to avoid them. FIG. 56 illustrates this. FIG. 56(a) indicates the case of insufficient acquisition time. FIG. 56(b) shows a case in which the problem could be solved by slowing the clock.
8.2 The Amplifier-ADC Interface
FIG. 57 ADC-amplifier interface: (a) Basic elements, (b) Performance
expected from ADC and amplifier. (Source: Analog Devices.)
Operational amplifiers nearly always are present in data acquisition systems, performing basic signal conditioning ahead of the ADC. Their interactions with ADCs affect system performance. Although many amplifiers are good at driving a variety of static loads, the switched nature of the ADC input stage can introduce problems with some amplifiers, especially the low-power, low-speed devices most likely to be used in 3 and 5 V systems. Using the simple model in FIG. 57(a), the load presented to the amplifier by the ADC input keeps switching abruptly between an open circuit and a series RC network connected to an internal voltage source. The opamp's response to the sudden load-current and impedance change depends on several parameters. Among them are the device's gain-bandwidth product, slew rate, and output impedance.
Selecting the appropriate drive amplifier for an ADC involves many considerations. Because the ADC drive amplifier is in the signal path, its error sources (both DC and AC) must be considered in calculating the total error budget.
Ideally, the AC and DC performance of the amplifier should be such that there is no degradation of the ADC performance. Achieving this rarely is possible, however; therefore, the effects of each amplifier error source on system performance should be evaluated individually.
Evaluating and selecting opamps based on the DC requirements of the system is a relatively straightforward matter. For many applications, however, it’s more desirable first to select an amplifier on the basis of AC performance (bandwidth, THD, noise, etc.). The AC characteristics of ADCs are specified in terms of SNR, ENOBs, and distortion. The drive amplifier should have performance better than that of the ADC so that maximum dynamic performance is obtained (see FIG. 57(b)). If the amplifier AC performance is adequate, the DC specifications should be examined in terms of system performance. Table 3-6 summarizes the ADC drive amplifier considerations.
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TABLE 6 ADC Drive Amplifier Considerations
Performance Requirements
Parameter AC performance DC performance General Bandwidth, settling time, harmonic distortion, total harmonic distortion, noise, THD + noise Gain, offset, drift, gain nonlinearity As a general principle, select first for AC performance, then evaluate DC performance. Always consult the data sheet for recommendations
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Other considerations in interfacing are the input clamping and protection, drive amplifier noise configurations, ADC reference voltage considerations, settling time considerations, and the like. Interfaces between data converters and digital signal processors are discussed in Section 5.