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6. ADC Architectures
Within the 1990s and the latter part of the 1980s, many architectures for A/D conversion have been implemented in monolithic form. Manufacturing process improvements achieved by mixed-signal product manufacturers have led to this unprecedented development, which was fueled by the demand from the product and system designers.
The most common ADC architectures in monolithic form are successive approximation, flash, integrating, pipeline, half flash (or subranging), two step, interpolative and folding, and sigma-delta (E-A). The following sections provide the basic operational and design details of these techniques.
While the E-A, successive approximation, and integrating types could give very high resolution at lower speeds, flash architecture is the fastest but with high power consumption. However, recent architecture breakthroughs have allowed designers to achieve a higher conversion rate at low power consumption with integral track and hold circuitry on a chip (McGoldrick, 1997). The AD9054 from Analog Devices is an example.
FIG. 25 Block diagram of successive approximation ADCs
6.1 Successive Approximation ADCs
The successive approximation register (SAR) ADC architecture has been used for decades and still is a popular and cost effective form of converter for sampling frequencies up to few MSPS. A simplified block diagram of an SAR ADC is shown in FIG. 25. On the start conversion command, all the bits of the successive approximation register are reset to 0 except the most significant bit (MSB), which is set to 1. Bit 1 is tested in the following manner. If the ADC output is greater than the analog input, the MSB is reset; otherwise, it’s left set. The next most significant bit then is tested by setting it to 1. If the digital/analog converter (DAC) output is greater than the analog input, this bit is reset; otherwise it’s left set. The process is repeated with each bit in turn. When all the bits have been set, tested, and reset or not as appropriate, the contents of the SAR correspond to the digital value of the analog input, and the conversion is complete.
An N-bit conversion takes N steps. On superficial examination, a 16-bit converter would seem to have a conversion time twice as long as an 8-bit one, but this is not the case. In an 8-bit converter, the DAC must settle to 8-bit accuracy before the bit decision is made, whereas in a 16-bit converter, it must settle to 16-bit accuracy, which takes a lot longer. In practice, 8-bit successive approximation ADCs can convert in a few hundred nanoseconds, while 16-bit ones generally take several microseconds.
The classic SAR ADC is only a quantizerm no sampling takes place--and for an accurate conversion, the input must remain constant for the entire conversion period. Most modern SAR ADCs are sampling types and have internal sample and hold so that they can process AC signals. They are specified for both AC and DC applications. An SHA is required in an SAR ADC because the signal must remain constant during the entire N-bit conversion cycle.
The accuracy of an SAR ADC depends primarily on the accuracy (differential and integral linearity, gain, and offset) of the internal DAC. Until recently, this accuracy was achieved using laser-trimmed thin-film resistors. Modern SAR ADCs utilize CMOS switched capacitor charge redistribution DACs. This type of DAC depends on the accurate ratio matching and the stability of on-chip capacitors rather than thin-film resistors. For resolutions greater than 12 bits, on-chip auto-calibration techniques, using an additional calibration DAC and the accompanying logic, can accomplish the same thing as thin-film laser-trimmed resistors, at much less cost. Therefore, the entire ADC can be made on a standard submicron CMOS process.
The successive approximation ADC has a very simple structure, low power, and reasonably fast conversion times (<1 MSPS). It’s probably most widely used ADC architecture and will continue to be used for medium-speed, medium-resolution applications.
Current 12-bit SAR ADCs achieve sampling rates up to about 1 MSPS, and 16-bit ones up to about 300 kSPS. Examples of typical state of the art SAR ADCs are the AD7892 (12 bits at 600 kSPS), the AD976/977 (16 bits at 100 kSPS), and the AD7882 (16 bits at 300 kSPS).
FIG. 26 Flash or parallel ADC block diagram
6.2 Flash Converter
Flash ADCs (sometimes called parallel ADCs) are the fastest ADCs and use large numbers of comparators. An N-bit flash ADC consists of 2 N resistors and 2 N -1 comparators arranged as in FIG. 26. Each comparator has a reference voltage 1 least significant bit (LSB) higher than that of the one below it in the chain. For a given input voltage, all the comparators below a certain point will have their input voltage larger than their reference voltage and a 1 logic output, and all the comparators above that point will have a reference voltage larger than the input voltage and a 0 logic output. The 2 N -1 comparator output therefore behaves like a mercury thermometer, and the output code at this point is sometimes called a thermometer code. Since 2 N -1 data output is not really practical, these are processed by a decoder to an N-bit binary output.
The input signal is applied to all the comparators at once, so the thermometer output is delayed by only one comparator delay from the input and the encoder N-bit output by only a few gate delays on top of that, so the process is very fast.
However, the architecture uses large numbers of resistors and comparators and is limited to low resolutions; if it’s to be fast, each comparator must run at relatively high power levels. Hence, the problems of flash ADCs include limited resolution, high power dissipation because of the large number of high-speed comparators (especially at sampling rates greater than 50 MSPS), and relatively large (and therefore expensive) chip sizes. In addition, the resistance of the reference resistor chain must be kept low to supply adequate bias current to the fast comparators, so the voltage reference has to source quite large currents (> 10 mA). In practice, flash converters are available up to 10 bits of resolution, but more commonly they have 8 bits of resolution. Their maximum sampling rate can be as high as 500 MSPS, and input full-power bandwidths are in excess of 300 MHz.
But, as mentioned earlier, full-power bandwidths are not necessarily full-resolution bandwidths. Ideally, the comparators in a flash converter are well matched both for DC and AC characteristics. Because the strobe is applied to all the comparators simultaneously, the flash converter is inherently a sampling converter. In practice, delay variations between the comparators and other AC mismatches cause a degradation in ENOB at high input frequencies. This is because the inputs are slewing at a rate comparable to the comparator conversion time.
The input to a flash ADC is applied in parallel to a large number of comparators. Each has a voltage-variable junction capacitance, and this signal-dependent capacitance results in all flash ADCs having reduced ENOB and higher distortion at high input frequencies. For more details, see Analog Devices (1996).
6.3 Integrating ADCs
The integrating ADC is a very popular architecture in applications where a very slow conversion rate is acceptable. A classic example is the digital multimeter.
All the converters discussed so far can digitize analog inputs at speeds of at least 10 kSPS. A typical integrating converter is slow relative to these high-speed converters. Useful for precisely measuring slowly varying signals, the integrating converter finds applications in low-frequency and DC measurement applications.
Integrating converters are based on an indirect conversion method. Here the analog input voltage is converted to a time period and later to a digital number using a counter. The integration eliminates the need for a sample/hold (S/H) circuit to "capture" the input signal during the measurement period. The two common variations of the integrating converter are the dual slope type and the charge balance or multislope type. The dual slope technique is very popular among instrument manufacturers because of its simplicity, low price, and better noise rejection. The multislope technique is an improvement on the dual slope method.
FIG. 27(a) shows a typical integrating converter. It consists of an analog integrator, a comparator, a counter, a clock, and control logic. FIG. 27(b) shows the circuit's charge (TI) and discharge (Tz) waveforms. The conversion is started by closing the switch and thereby connecting the capacitor, Clnt, to the unknown input voltage, Vi,, through the resistor, R. This results in a linear ramp at the integrator output for a fixed period, TI, controlled by the counter. The control circuit then switches the integrator input to the known reference voltage, Vref, and the capacitor discharges until the comparator detects that the integrator has reached the original starting point. The counter measures the amount of time taken for the capacitor to discharge.
Because the values of the resistor, the integrating capacitor, and the frequency of the clock remain the same for both the charge and discharge cycles, the ratio of the charge time to the discharge time is equal to the ratio of the reference voltage to the unknown input voltage. The absolute values of the resistor, capacitor, and the clock frequency therefore don’t affect the conversion accuracy. Furthermore, any noise on the input signal is integrated over the entire sampling period, which imparts a high level of noise rejection to the converter.
FIG. 27 Diagrams of an integrating ADC: (a)Block diagram, (b)Timing diagram
By making the signal integration period an integral multiple of the line frequency period, the user can obtain excellent line frequency noise rejection.
A charge balance integrating converter incorporates many of the elements of the dual slope converter but uses a free-running integrator in a feedback loop.
The converter continuously attempts to null its input by subtracting precise charge packets when the accumulated charge exceeds a reference value. The frequency of the charge packets (the number of packets per second) the converter needs to balance the input is proportional to that input. Clock-controlled synchronous logic delivers a serial output that a counter converts to a digital word in the circuit.
Integrating converters in monolithic form typically are used in digital voltmeters due to their high resolution properties. Hybrid integrating converters with 22-bit resolutions were introduced to the market in the late 1980s. It therefore is possible to expect higher resolutions in the monolithic market as well. There could be many variations of this technique as applied to digital multimeters, and Kularatna (1996) is suggested for details.
6.4 Pipeline Architectures
FIG. 28 A pipeline system
FIG. 29 A two-step ADC pipeline: (a) Block diagram, (b)Clock waveform
and related activities.
The concept of a pipeline, often used in digital circuits, can be applied in the analog domain to achieve higher speed where several operations must be performed serially. FIG. 28 shows a general (analog or digital) pipeline system. Here, each stage carries out an operation on a sample, provides the output for the following sampler, and once that sampler has acquired the data, begins the same operation on the next sample. Thus, at any given time, all the stages are processing different samples concurrently; hence, the throughput rate depends only on the speed of each stage and the acquisition time of the next sampler.
To arrive at a simple example of an analog pipeline, consider a two-step ADC, where four operations (coarse A/D conversion, interstage D/A conversion, subtraction, and fine A/D conversion) must be performed serially. As such, the ADC cannot begin to process the next sample until all four operations are finished.
Now, suppose an SHA is interposed between the subtractor and the fine stage, as shown in FIG. 29, so that the residue is stored before fine conversion begins. Thus, the front-end SHA, the coarse ADC, the interstage DAC, and the subtractor can start processing the next sample while the fine ADC operates on the previous one, allowing potentially faster conversion. More details on pipeline architectures can be found in Louzon (1995).
FIG. 30 8-bit subranging ADC
FIG. 31 Pipeline subranging ADC with a digital error correction.
TABLE 3
Key Specifications of the AD9042. (Analog Parameter Value Input range Input impedance Effective input noise SFDR at 20 MHz input SINAD (S/N +D) at 20 MHz input Digital outputs Power supply Power dissipation Fabrication 1 V peak-to-peak, Vcm --+2.4 V 250 fl to Vcm 0.33 LSBs rms 80 dB minimum 67 dB TTL compatible Single +5 V 595 mW High-speed dielectrically isolated complementary bipolar process
6.5 Half-Flash ADCs
Although it’s not practical to make them with high resolution, flash ADCs often are used as subsystems in "subranging" ADCs (sometimes known as half-flash ADCs), which are capable of much higher resolutions (up to 16 bits). A block diagram of an 8-bit subranging ADC based on two 4-bit flash converters is shown in FIG. 30. Although 8-bit flash converters are readily available at high sampling rates, this sample will be used to illustrate the theory.
The conversion process is done in two steps. The four most significant bits are digitized by the first flash (to better than 8-bit accuracy) and the 4-bit binary output is applied to 4-bit DAC (again, better than 8-bit accuracy). The DAC output is subtracted from the held analog input, and the resulting residue signal is amplified and applied to the second 4-bit flash. The output of the two flash converters are combined into a single 8-bit binary output word. If the residue signal range does not exactly fill the range of the second flash converter, nonlinearities and perhaps missing codes 1 will result.
Modern subranging ADCs use a technique called digital correction to eliminate problems associated with the architecture of FIG. 30. A simplified block diagram of a 12-bit digitally corrected subranging ADC is shown in FIG. 31.
An example of such a practical ADC is the AD9042 from Analog Devices, a 12-bit, 41 MSPS device. Key specifications of the AD9042 are given in Table 3.
Note that a 6-bit and 7-bit ADC have been used to achieve an overall 12-bit output. These are not flash ADCs but utilize a magnitude-amplifier (MagAmp ) architecture. (See Section 4 in Analog Devices (1996) for MagAmp basics.)
If there were no errors in the first-stage conversion, the 6-bit "residue" signal applied to the 7-bit ADC by the summing amplifier would never exceed one-half the range of the 7-bit ADC. The extra range in the second ADC is used in conjunction with the error correction logic (usually just a full adder) to correct the output data for most of the errors inherent in the traditional uncorrected subranging converter architecture. It’s important to note that the 6-bit DAC must be better than 12-bit accurate, because the digital error correction does not correct for DAC errors. In practice, "thermometer" or "fully decoded" DACs using one current switch per level (63 switches in the case of a 6-bit DAC) often are used instead of a "binary" DAC to ensure excellent differential and integral linearity and minimum switching transients (Analog Devices, 1996). The second SHA delays the held output of the first SHA while the first-stage conversion occurs, thereby maximizing throughput. The third SHA "deglitches" the residue output signal, allowing a full conversion cycle for the 7-bit ADC to make its decision (the 6-and 7-bit ADCs in the AD9042 are bit-serial MagAmp ADCs, which require more settling time than a flash converter). Additional shift registers in series with the digital output of the first-stage ADC ensure that its output ultimately is time-aligned with the last 7 bits from the second ADC when their outputs are combined in the error correction logic. A pipeline ADC therefore has a specified number of clock cycles of latency m pipeline delay--associated with the output data. The leading edge of the sampling clock (for sample, N) is used to clock the output register, but the data that appears as a result of that clock edge corresponds to sample N-L, where L is the number of clock cycles of latency; in the case of the AD9042, two clock cycles of latency.
The error correction scheme described previously is designed to correct for errors made in the first conversion. Internal ADC gain, offset, and linearity errors are corrected as long as the residue signal falls within the range of the second-stage ADC. These errors won’t affect the linearity of the overall ADC transfer characteristic. Errors made in the final conversion, however, translate directly as errors in the overall transfer function. Also, linearity errors or gain errors either in the DAC or the residue amplifier won’t be corrected and will show up as nonlinearities or non-monotonic behavior in the overall ADC transfer function.
So far, we have considered only two-stage subranging ADCs, as these are easiest to analyze. There is no reason to stop at two stages, however. Three-pass and four-pass subranging pipeline ADCs are quite common and can be made in many different ways, usually with digital error correction.
6.6 Two-Step Architectures
The exponential growth of power, die area, and input capacitance of flash converters as a function of resolution makes them impractical for resolutions above 8 bits in general. These resolutions call for topologies that provide a more relaxed trade-off among the parameters. Two-step architectures trade speed for power, area, and input capacitance.
In a two-step ADC, first a coarse analog estimate of the input is obtained to yield a small voltage range around the input level. Subsequently, the input level is determined with higher precision within this range. FIG. 32(a) illustrates a two-step architecture consisting of a front-end SHA, a coarse flash ADC stage, a DAC, a subtractor, and a fine flash ADC stage. We describe its operation using the timing diagram shown in the FIG. 32(b). For t < t~, the SHA tracks the analog input. At t—t1, the SHA enters a hold mode and the first flash stage is strobed to perform the coarse conversion.
The first stage then provides a digital estimate of the signal held by the SHA (VA), and the DAC converts this estimate to an analog signal (VB), which is a coarse approximation of the SHA output. Next, the subtractor generates an output equal to the difference between VA and V8 (Vc, called the residue), which is subsequently digitized by the fine ADC. Comparison of timing in flash and two-step architectures is shown in FIG. 32(c).
FIG. 32 Two-step architecture: (a) Block diagram, (b) Timing, (c) Comparison
of timing in flash and two-step architectures.
A two-step ADC need not employ two separate flash stages to perform the coarse and fine conversions. One stage can be used for both; and such an architecture, shown in FIG. 33, is called recycling architecture.
Here, during the coarse conversion, the flash stage senses the front-end SHA output, VA, and generates the coarse digital output. This digital output then is converted to analog by the DAC and subtracted from VA by the subtractor. During fine conversion, the subtractor output is digitized by the flash stage. Note that, in this phase, the ADC full-scale voltage must be equal to that of the subtractor output. Therefore, for proper fine conversion, either the ADC reference voltage must be reduced or the residue must be amplified.
While reducing area and power dissipation by roughly a factor of 2 relative to two-stage ADCs, recycling converters suffer from other limitations. The converter must now employ either low-offset comparators (if the subtractor has a gain of 1), inevitably slowing down the coarse conversion, or a high-gain subtractor, increasing the interstage delay. This is in contrast with two-stage ADCs, where the coarse stage comparators need not have a high resolution and hence can operate faster.
6.7 Interpolating and Folding Architectures
To maintain the one-step nature of the flash-type architectures, without adding sample-and-hold circuits to the ADC, several other architectures are available. Among these techniques, interpolation and folding have proven quite beneficial. Earlier, these techniques had been applied predominantly to bipolar circuits; recently CMOS devices have entered the market.
As a comprehensive discussion on these techniques is beyond the scope of this section, only basic approach in the design is discussed here.
FIG. 33 Recycling ADC architecture
6.7.1 Interpolating Architectures
To reduce the number of preamplifiers at the input of a flash ADC, the difference between the analog input and each reference voltage can be quantized at the output of each preamplifier. This is possible because of the finite gain; hence, nonzero linear input range of typical preamplifiers used as the front end of comparators.
We illustrate this concept in FIG. 34(a). In FIG. 34(a), preamplifiers A1 and A2 compare the analog input with Vr1 and Vr2, respectively. In FIG. 34(b), the input/output characteristics of A1 and A2 are shown. Assuming zero offset for both preamplifiers, we note that Vxl = Vrl if Vin "-Vrl, and VX2 = VY2 if Vin --Vr2. More important, VX2 = Vy1 if Vin --Vm = (Vrl "+" Vr2)/2; that is, the polarity of the difference between Vx2 and Vr1 is the same as that of the difference between Vin and Vm.
The preceding observation indicates that the equivalent resolution of a flash stage can be increased by "interpolating" between the output of preamplifiers.
For example, FIG. 34(c) shows how an additional latch detects the polarity of the difference between the single-ended output of two adjacent preamplifiers.
Note that in contrast with a simple flash stage, this approach halves the number of preamplifiers but maintains the same number of latches.
FIG. 34 Interpolating architecture: (a) Basic block, (b) Interpolation
between output of two amplifiers, (c) Interpolation in a flash ADC
The interpolation technique of FIG. 34(c) substantially reduces the input capacitance, power dissipation, and area of flash converters, while preserving the one-step nature of the architecture. This is possible because all the signals arrive at the input of the latches simultaneously and hence can be captured on one clock edge. Since this configuration doubles the effective resolution, we say it has an interpolation factor of 2. For further details on this architecture, see below.
6.7.2 Folding Architectures
Folding architectures have evolved from flash and two-step topologies.
Folding architectures perform analog preprocessing to reduce hardware while maintaining the one-step nature of flash architectures.
The basic principle in folding is to generate a residue voltage through analog preprocessing and subsequently digitize that residue to obtain the least significant bits. The most significant bits can be resolved using a coarse flash stage that operates in parallel with the folding circuit and, hence, samples the signal at approximately the same time that the residue is sampled. FIG. 35 depicts the generation of residue in two-step and folding architectures. In a two-step architecture, coarse A/D conversion, interstage D/A conversion, and subtraction must be completed before the proper residue becomes available. In contrast, folding architectures generate the residue "on the fly" using simple wideband stages.
To illustrate this principle, we first describe a simple, ideal approach to folding. Consider two amplifiers, A1 and Ae, with the input/output characteristics depicted in FIG. 36(a). The active region of one amplifier is centered around (Vr2 + Vr1)/2 and that of the other around (Vr3 -Jr-Vr2)/2, and Vr3 --Vr2 = Vr2-Vrl. Each amplifier has a gain of 1 in the active region and 0 in the saturation region. If the outputs of the two amplifiers are summed, the "folding" characteristic of FIG. 36(b) results, yielding an output equal to Vin-Vrl for Vrl < Vin < Vr2 and (-Vin -[-" Vr2--[-A) for Vr2 < Vin < Vr3, where A is the value of the summed characteristics at Vin --Vr2. If Vrl, Vr2, and Vr3 are the reference voltages in an ADC, then these two regions can be viewed as the residue characteristics of the ADC for Vrl < Vin < Vr3. TO understand why, we compare this characteristic with that of a two-step architecture, as shown in FIG. 36(c). The two characteristics are similar except for a negative sign and a vertical shift in the folding output for Vr2 < Vin < Vr3. Therefore, if the system accounts for the sign reversal and level shift, the folding output can be used as the residue for fine digitization.
FIG. 35 Generation of residue: (a) Two-step architecture, (b) Folding
architecture
FIG. 36 The concept of folding: (a) Input/output characteristics of two
amplifiers, (b) Sum of characteristics in (a), (c) Residue in two-step
ADC
FIG. 37 Folding circuit and its characteristics: (a) Circuit, (b) Characteristics
FIG. 37(a) shows an implementation of folding. Here, four differential pairs process the difference between Vin and Vr1 ..... Vr4, and their output currents are summed at nodes X and Y. Note that the outputs of adjacent stages are added with opposite polarity; For example, as Vin increases, Q1 pulls node X low while Q2 pulls node Y low. Current source 15 shifts Vy down by IR. To explain the operation of the circuit, we consider its input/output characteristics, plotted in FIG. 37(b). For Vin well below Vrl, Q1-On are off, Q5-Q8 are on, 12 and 14 flow through Rcl, and 11,13, and 15 flow through Rc2. As Vin exceeds Vrl by several Vr, Q5 turns off, allowing Vx and Vy to reach Vmin and Vmax, respectively. As Vin approaches Vr2, Q2 begins to turn on and the circuit behaves as before. Considering the differential output, Vx -Vr., we note that the resulting characteristic exhibits folding points at (Vrl + Vr2)/2, (Vr2 --k-Vr3)/2, and so forth. As Vin goes from below Vrl to above Vr4, the slope of Vx-Vr, changes sign four times; hence, we say the circuit has a folding factor of 4.
The simplicity and speed of folding circuits have made them quite popular in A/D converters, particularly because they eliminate the need for sample-and-hold amplifiers, D/A converters, and subtractors. Nevertheless, several drawbacks limit their use at higher resolutions.
6.8 Sigma-Delta Converters
Sigma-Delta analog/digital converters (E-A ADCs) have been known for nearly 30 years, but only recently has the technology (high-density digital very large-scale ICs) existed to manufacture them as inexpensive monolithic integrated circuits. They are used in many applications where a low-cost, low-bandwidth, high-resolution ADC is required.
The literature contains innumerable descriptions of the architecture and theory of E-A ADCs (Candy and Temes, 1992). As a text of this nature is not appropriate for describing their mathematical analysis and background, this section has been written to classify the subject. A practical monolithic E-A ADC contains very simple analog circuit blocks (a comparator, a switch, and one or more integrators and analog summing circuits) and quite complex digital computational circuitry. The circuitry consists of a digital signal processor that acts as a filter (generally, but not invariably, a low-pass filter). It’s not necessary to know how the filter works to appreciate what it does. To understand how a Y;-A ADC works, one should be familiar with the concepts of oversampling, noise shaping, digital filtering, and decimation. We briefly discuss these concepts in E-A converters.
6.8.1 Key Concepts Behind the sigma-delta ADC
FIG. 38 shows the transfer characteristic of a 3-bit unipolar sigma-delta ADC. The input to an ADC is analog and is not quantized, but its output is quantized. The transfer characteristic therefore consists of eight horizontal steps (when considering the offset, gain, and linearity of an ADC, we consider the line joining the midpoints of these steps). Digital full scale (all ones) corresponds to 1 LSB below the analog full scale (the reference or some multiple of it). This is because, as mentioned previously, the digital code represents the normalized ratio of the analog signal to the reference, and if this were unity, the digital code would be all zeros and 1 in the bit above the MSB. The (ideal) ADC transitions take place at 0.5 LSB above 0 find thereafter every LSB, up to 1.5 LSB below analog full scale. Since the analog input to an ADC can take any value but the digital output is quantized, there may be a difference of up to 0.5 LSB between the actual analog input and the exact value of the digital output. This is known as the quantization error or quantization uncertainty. In AC (sampling) applications, this quantization error gives rise to quantization noise. If we apply a fixed input to an ideal ADC, we always will obtain the same output and the resolution will be limited by the quantization error.
Suppose, however, that we add some AC (dither) to the fixed signal, take a large number of samples, and prepare a histogram of the results. We will obtain something like the result in FIG. 39. If we calculate the mean value of a large number of samples, we will find that we can measure the fixed signal with greater resolution than that of the ADC we are using. This procedure is known as oversampling.
The AC (dither) that we add may be a sine wave, a triangular wave, or Gaussian noise (but not a square wave); and with some types of sampling ADCs (including sigma-delta ADCs), an external dither signal is unnecessary, since the ADC generates its own. Analysis of the effects of differing dither waveforms and amplitudes is complex and, for the purposes of this section, unnecessary. What we need to know is that with the simple oversampling described here, the number of samples must be doubled for each bit of increase in resolution.
FIG. 38 Transfer characteristics of a 3-bit unipolar ADC
FIG. 39 Oversampling
FIG. 40 Sampling ADC quantization noise
FIG. 41 Oversampling and digital filtering: (a) Block diagram, (b) Output
vs. frequency.
If, instead of a fixed DC signal, the signal that we are oversampling is AC, then it’s not necessary to add a dither signal to it to oversample, since the signal is moving anyway. (If the AC signal is a single-tone, harmonically related to the sampling frequency, dither may be necessary, but this is a special case.) Consider the technique of oversampling with an analysis in the frequency domain. Where a DC conversion has a quantization error of up to 1/2 LSB, a sampled data system has quantization noise. As we already have seen, a perfect classical N-bit sampling ADC has an rms quantization noise of q/~-~ uniformly distributed within the Nyquist band of DC to fs/2 (where q is the value of an LSB and fs is the sampling rate), giving us an SNR of (6.02N -t-1.76) dB with full-scale sine wave inputs (e.g., equation (3.1); see FIG. 40). If the ADC is less than perfect and its noise is greater than its theoretical minimum quantization noise, then its effective resolution will be less than N bits.
Its actual resolution (often known as its effective number of bits, ENOB) will be defined by equation (2). If we choose a much higher sampling rate (K times fs, as in FIG. 41(a)), the quantization noise is distributed over a wider bandwidth as shown in FIG. 41 (b). If we then apply a digital low-pass filter to the output, we remove much of the quantization noise but don’t affect the wanted signal, so the ENOB is improved. We have performed a high-resolution A/D conversion with a low-resolution ADC. Since the bandwidth is reduced by the digital output filter, the output data rate may be lower than the original sampling rate and still satisfy the Nyquist criteria. This may be achieved by passing every Mth result to the output and discarding the remainder, a process is known as decimation by a factor of M. Here, M can have any integer value, provided that the output data rate is more than twice the signal bandwidth. Decimation causes no loss of information ( FIG. 42). As shown in FIG. 42, after sampling at fs and filtering, the output data rate may be reduced to fs/M with no loss of information.
6.8.2 Block Diagram of a sigma-delta ADC
Oversampled sigma-delta ADCs in recent years have become more prevalent for high-accuracy, 12 bit to beyond 22 bit, A/D conversion of DC through moderately high (hundreds of kHz) AC signals. Their greatest advantage is that they trade greatly reduced analog circuit accuracy requirements for increased digital circuit complexity. This is a distinct advantage for 1-2 micron and submicron very large-scale integrated (VLSI) digital circuit technologies. VLSI circuit techniques can achieve circuit densities of hundreds of thousands of gates, allowing complex digital filters to be integrated on the chip. The result is high precision at low cost.
FIG. 42 Decimation process ---After sampling at fs and filtering, the
output data rate may be reduced to fs/M with no loss of information
FIG. 43 Oversampled sigma-delta ADC
The basic oversampled sigma-delta A/D converter ( FIG. 43) is an integrating A/D converter. The single-bit feedback D/A converter output is subtracted from the analog input signal, Vin, in the summing amplifier. The resulting error signal from the summing amplifier output is low-pass filtered by the integrator and the integrated error signal polarity is detected by the single comparator. This comparator effectively is a 1-bit A/D converter.
The output of the comparator drives the 1-bit DAC to a 1 or 0 to a 1, if during the previous sample time the integrator output was detected by the comparator as being too low, that is, below 0 V; a 0, if the difference detected during the previous sample was too high, that is, above 0 V reference of the comparator). The 1-bit D/A converter, as in successive approximation A/D converters, provides the negative feedback. This negative feedback for a 1 in the D/A converter always is in a direction to drive the integrator output toward 0 V. The D/A converter output for a 1 input would be the reference voltage. The reference voltage would be equal to or exceed the expected full-scale analog input signal voltage. Then, for a small value of gin, the integrator would take many clock pulses to cross 0 V, after a single 1 was generated, during which time the comparator is sending zeros to the digital filter. If Vin were at full scale, the integrator would cross 0 every clock time and the comparator output would be a string of alternate ones and zeros. The digital filter's function is to determine a digital number at its output that is proportional to the number of ones in the previous bit stream from the comparator. Various types of digital filters are used to perform this computational function, which is the most complex function in this type of D/A converter. However, complex digital computations can be performed readily in a VLSI circuit.
Oversampled converters sample at much higher rates than the Nyquist rate.
The oversampling ratio is equal to the actual sampling rate divided by the Nyquist rate. The oversampling rate can be hundreds to thousands of times the analog input signal frequency bandwidth. Since each sample is in a 1-bit low accuracy conversion, sampling rates can be very high.
In cases where antialiasing filtering is required on the input analog signal, the filter does not require the sharp cutoff characteristics as would be required to limit broadband signals prior to a successive approximation-type A/D converter operating at or near a small multiple of the Nyquist sampling rate. The reason is that the oversampling rate is many times the Nyquist rate. Therefore, a simple RC filter is adequate to prevent aliasing. The input filter can pass frequencies many times higher than the frequencies of interests before filter cutoff is required. The bandwidth of signals converted can be increased significantly by a sigma-delta A/D converter at a given clock sampling rate by using a multibit A/D and D/A converter rather than a single-bit A/D and D/A converter. Digital filter design is another variable affecting the bandwidth of signals that can be accurately converted for a given oversampling rate.
However, the greatest advantage of an oversampled sigma-delta converter is that it requires only a single-bit A/D and D/A converter with a relatively inaccurate differential summing amplifier and integrator (low-pass filter). These analog circuits are much easier to implement in a digital VLSI circuit than the accurate analog circuits required in parallel-and successive-approximation A/D converters that require precision resistors or capacitors. This is especially true when accuracies exceed 12 bits.
Based on the preceding description, we can show that the quantized signal bounces between two levels, keeping its mean equal to the input, when the input to the modulator is a DC signal. FIG. 44 shows the quantized signal and the integrated output when the input signal is 3 delta /7 above 0 for a quantization level of a. The figure indicates that the oscillation may be repetitive (it returns to its starting condition after seven clock periods). The frequency of repetition depends on the input level.
FIG. 44 Waveforms in a sigma-delta circuit for a constant input situated
at 3 delta /7 above a quantization level: (a) Quantized signal and input,
(b) Integrator output.
By using more than one integration and summing stage in the sigma-delta modulator, higher orders of quantization noise shaping and better ENOB for a given oversampling ratio can be achieved (Analog Devices, 1995). A block diagram of a second-order sigma-delta ADC is shown in FIG. 45.
FIG. 45 Second-order sigma-delta ADC
6.9 Self-Calibration Techniques
Integral linearity of data converters usually depends on the matching and linearity of integrated resistors, capacitors, or current sources; and it’s typically limited to approximately 10 bits with no calibration. For higher resolutions, means must be sought that can reliably correct nonlinearity errors. This often is accomplished by either improving the effective matching of individual devices or correcting the overall transfer characteristics. Since high-resolution A/D converters typically employ a multistep architecture, they often impose two stringent requirements: small integral nonlinearity in their interstage DACs and precise gain (usually a power of 2) in their interstage subtractors/amplifiers. These constraints in turn demand correction for device mismatches if resolutions above 10 bits are required.
ADC calibration techniques can be in two forms: use of analog processing techniques for correction of non-idealities and digital calibration techniques. A description of these techniques is beyond the scope of this section.
6.10 Figure of Merit for ADCs
The demand for lower power-dissipating electronic systems has become a challenge to the IC designer, including designers of ADCs. As a result, a figure of merit was devised by the ISSCC 1 Program Committee to compare available and future sampling-type ADCs. The figure of merit (FOM) is based on an ADC's power dissipation, its resolution, and its sampling rate. The FOM is derived by dividing the device's power dissipation (in watts) by the product of its resolution (in 2 n bits) and its sampling rate (in hertz). The result is multiplied by 10^12. This is expressed by the equation
FOM = (PD/ R×SR)^10^12
where PD = Power dissipation (in watts); R = Resolution (in 2 n bits); SR = Sampling rate (in hertz).
Therefore, a 12-bit ADC sampling at 1 MHz and dissipating 10 mW has a figure of merit rounded off to 2.5. This figure of merit is expressed in the units of picojoules of energy per unit conversion (pj)/conversion. For details and a comparison of performance of some monolithic ICs, see Goodenough (1995).