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AMAZON multi-meters discounts AMAZON oscilloscope discounts . Focusing on some real-world issues … This is a compilation of articles written on myriad Switching Power topics. The purpose of these articles is to focus on specific issues that we have encountered over many years in the industry, working across several continents.
Sounds Like Worst-case, But There's Danger Lurking in the Middle SMPS-guru describes a PC power supply failure that seemed widespread in Japan, but seldom occurred in the U.S. Was it something in the sushi? he asks. It turns out, the failures are related to the way components are specified and tested. This amusing and instructive piece kicks off a new column on power supply design. SMPS-guru's comments will appear monthly on various Blogs. In hindsight, this probably seemed routine enough to inspire some complacency. An OEM PC power supply was all set to go into full production. The Design Integrity Team put it through its paces. Maximum loads were applied at extreme ambients. Stress levels were verified, life predictions matched up, vibration testing, EMI, safety etc., were a cinch. The product was released and no problem was noticed in the several thousand units first shipped to the American market. Then the failures started to show up in droves. All came mysteriously from Japan. Must've been something in the sushi! What happened was actually so simple that several people must have kicked themselves (and each other). Turns out this power supply had not been tested in Standby mode! Why test in Standby mode?? That's only a handful of watts compared to the 550 W max load. However, when fully operational, the power supply had a fan running off its main 12 V output. In Standby mode the fan stopped as all the outputs collapsed. Well, all outputs but one! A small standby integrated converter was also present on-board delivering a low power 5 V housekeeping rail. Unfortunately, it was left freestanding by an otherwise experienced engineer who thought its low power wasn't worth his while. Its temperature in Standby mode thus made history. But we also learned that the Japanese actually initiate the Standby function of their PCs rather than leaving the computer idle, as Americans would. Also remember that a buck converter's input capacitor sees the maximum RMS current at D = 0.5. If your input voltage range is, say, 15 V to 48 V, and you test it "diligently" at both the input corners, you still may never know how long your capacitor will really last. Or take an interleaved buck converter with two independent channels running out of phase. Here we are actually relying on both channels being fully loaded to reduce the input capacitor's RMS current. But in fact this current can be even higher if one channel is unloaded. Coming to magnetics, we also now know that the surface temperature of a core-loss dominated choke means nothing if there is a variable-speed fan present. Remember a few years ago when major manufacturers had field returns, in which the powdered iron chokes had virtually returned to their original powdered form because of prolonged core temperatures. This had then prompted vendors to scramble to characterize life expectancy. Try www.micrometals.com for more information. Editor's Note: SMPS-guru, author of the popular Analog series on EMI in power supplies, has over 35 years of design experience. Loop Design Sometimes Compensates for Lower-quality Switchers SMPS-guru is back with a new installment of his popular power supply design column. The question he asks is how to make up for the erratic quality of the 3842 and 3844 switching power supply controllers now on the market. An adjustment of the RC components in the hysteresis loop allowed a power supply company to safely utilize the batch lot of jittery components they were stuck with - some 50,000 of them. The 3842/43/44/45 series of pulse width modulators are possibly the most popular controllers for off-line applications for several years now. Originally from Unitrode (now Texas Instruments, "TI"), I can find 'clones' from at least 12 more semiconductor companies on the web (see if you can better the count). The list may in fact be quite endless. Their quality is however often questionable, though I do admit that their Application Information seems all rather well written (hmmm, but did I read that somewhere else?). Practically speaking these 'equivalents' can differ quite a bit. At one time we even had basic functionality problems due to an insurmountable jitter from an 'alternate source' part. No amount of decoupling on any pin was helping, and it was thus obvious that it was the result of an internal noise feedthrough from the driver stage to the clock, leading to premature pulse termination and unpredictable frequency. The 3844 from the slightly more expensive vendor worked perfectly on the same board and was in fact being shipped out in millions (this was a flyback for a very well-known computer manufacturer). Now trying to return the 50,000 jittery devices to the equally well-known (though now clearly jittery) vendor was met with the familiar 'show me where in the datasheet' attitude. I did manage to band-aid the problem shortly after my arrival at the Singapore-based company I worked for, and they did manage to slip the bad parts into their high volume production, with no future 'ppm' issues either. Though understandably they didn't return to the previous vendor to renew their learnings on what constitutes a 'guaranteed spec' and what is not. This was the simple logic I applied to solve the problem: in the 3844, the clock pulse is generated by a simple RC charge-discharge cycle taking place between two fixed voltage thresholds. At the falling edge of the PWM pulse, noise was getting injected onto the ramp and could fool the internal comparator into 'thinking' that the timing capacitor had reached its upper threshold (see Fgr. 1), at which point the discharge cycle would start prematurely (not shown in figure for reasons of clarity). Now what if we decreased the discharge time by decreasing the C, but simultaneously increased the R to maintain the same frequency? Now the ramp is actually slightly lower at the instant where the falling edge of the PWM pulse occurs. We can see that the noise margin has thus improved. Fgr. 1: Noise in the 3844 We must remember that normally, if there is a major change on the primary side of an off-line power supply, we definitely need a fresh approval from safety agencies. But this minor change in the RC combination apparently just merited a notification. End of story. Re-inventing the Wheel ... as a Square We've all seen renderings of the disconnect between marketing, engineering, and customers in product development - using a child's backyard swing as the example. What marketing requested shows a three-tiered swing, with cushions and lollypop dispensers. What engineering came up with shows a rocket-propelled platform, springing back-and-forth through a steel-reinforced tunnel. What the customer really wanted, of course, was a truck tire hanging by a rope from a tree limb. This month, SMPS-guru comments on some magnificently-designed power supplies. A lot has been said about not reinventing the wheel. But how about not repeating errors? 'Errors' are like wheels that we shouldn't even have tried to invent, let alone re-invent, because this wheel was probably square in shape to start with, and there was never any chance of it succeeding. Yet some may be surprised to know how often this may already have happened. And will happen again. It's just that we don't hear much about it. If we had inside knowledge, we would often find that such projects usually had impeccable beginnings. Clear design goals, a thoughtful strategy, solid design trade-offs, but then one embarrassing turn to the left. The result was a product that had no known identifiable sire, and in fact no one even remembered ever having worked on it! We all know that marketing, given its nature, always tries to emphasize successes. And no doubt they would be working overtime to gloss this one up. But engineers, with an eye on not repeating known errors in future development, are always keenly interested in what should or could have been done. If only they knew. Here is a list of some eyebrow raising situations which caught my attention over the years. The examples leave one incredulous. Example 1 A telecom project required a rack of several 3000 W Power Factor Corrected (PFC) hot-pluggable power supplies. Two brilliant teams went about it, one writing C++ code and the other designing the power sections and the backplane. This was to operate off a 3-phase AC mains supply. The engineers thought the best way out was to parallel three single phase 1000 W power-trains; that is, each power-train would be running off a different input Phase and the common Neutral. In doing so, the required minimum voltage rating of the FET switches would be the usual 450 V or so, as for any single-phase PFC stage, rather than other techniques which would usually require FETs with roughly twice the voltage rating. The project did get completed. Then the Marketing guys appeared and informed them that they just couldn't sell it -!! Because in many countries and areas, a 3-phase incoming supply point does not even include the Neutral wire (which in any case is not even designed to carry that much of return current either). This was a complete dead-end. But couldn't the Marketing guys have got, involved a little earlier? Say about 2 years before the project came to a head? Example 2 Users of a control IC meant for a Flyback topology should recognize that the maximum allowable duty cycle should never be set to 100%. A 100% duty cycle basically means the switch is no longer switching, and could just end up staying ON permanently. So if the output voltage is low, and the IC is trying to get it to rise by increasing the duty cycle 'D', and if D is 100%, there is now unfortunately zero available time for the current to freewheel into the output. So how can the output ever rise up try as hard as the controller insists? Yes such an IC has unfortunately been released into the general market. Look around! Example 3: Another product is a fairly popular off-line switcher IC family meant for Flyback applications. In an off-line case, the value of Dmax has several more implications. Here we must recall that the earlier generation of this switcher family had a maximum duty cycle of about 67%. When the next generation was conceived, the one-man product-definition team heuristically assigned a Dmax of 78%. His idea was that by 'allowing' a wider input current pulse, we would automatically get a lower current pedestal, and this would enhance the 'power capability' of his device (since this figure was being based purely on current limit, not on dissipation). This design strategy could actually have succeeded. But there is a catch. Let us consider what happens if we just remove the input power. By allowing the duty cycle to go up to such a high level, the momentary peak currents actually increase much more now, as compared to a case where the Dmax is set lower. This has severe implications on the transformer, since its size is related to the saturation level. There are also some other subtle issues. For example, it can be shown that the dissipation in the zener clamp can also go up significantly, thus worsening the overall efficiency. So the 'advantage' if any, turned out to be an illusion. Example 4: The popular 3842/3844 series I wrote about earlier, despite its popularity was apparently hastily conceived. Here we actually have a current mode controller that has no built-in slope compensation!! One would think that everything required for a particular topology should be inherent in the design. After all, we don't buy a bicycle from a store and then go out looking for a pair of tires for it! In this case we do just that. Example 5: One of the first semiconductor companies to come up with ICs for implementing a boost PFC pre-regulator had got it all wrong, and they admitted that to us privately: You can never hope to do proper sine wave shaping with peak current sensing! You need to do average current mode control, because it’s the average current drawn that forms the input current waveshape. Their competitor understood this, and so despite having broken in later, they quickly became the market leaders in PFC ICs. The former company changed hands, and is virtually unknown as a separate entity today. The Mighty Zener We’re by now sadly conditioned to expecting that nothing good is ever going to come our way, at least not easily and cheaply, writes SMPS-guru in the latest installment of his power supply design column. Surprise, surprise: The gate-source zener on your power FET (a couple of cents) can really save your bacon on safety issues. Looking at any typical off-line power converter, we will usually find a controller IC driving a high voltage FET. At the gate, besides the usual pull-down resistor to (primary) ground, we may also see a paralleled 500 mW/18 V zener diode. Yes, this diode does cost a few cents, but omitting it can be even more costly! This is just one of those examples of minor 'details' that will ultimately distinguish a bad power supply design from a really good one. On the face of it, this zener does look as if it’s there simply to 'protect' the gate oxide layer under various transients and noise spikes that may be encountered in the field. But while the effects of this one single component can be subtle, they can be dramatically helpful. This is admittedly a rare situation, especially in power conversion, where we are by now sadly conditioned to expecting that nothing good is ever going to come our way, at least not easily and cheaply enough, without some sort of indirect or unforeseen price to pay somewhere along the way. In fact, here too, we do have our share of some rather reflex-action pessimism abounding. People still seek to question the basic wisdom and validity of this rather crucial zener. But let us start off by first describing how I personally encountered this issue. The Singapore based design-cum-manufacturing outfit I worked in at that time had a policy of never (knowingly) putting in even one superfluous 1-cent component. They considered that equivalent to 'shipping free parts with every power supply.' They understood that at their current manufacturing volumes, they could probably hire another power supply design engineer for every zener diode they could eliminate from the schematic. Yet even they couldn't ultimately avoid this rather stubborn 'gate-source' zener. Note that this is actually a 'gate to ground' zener, because there usually is a current sense resistor between source and ground. The trouble actually started after their first manufacturing sample had been built with no such zener in place. It was submitted for the mandatory UL1950 safety approval. At the test house, various abnormal tests were carried out. In some of these tests the switching FET exploded. And in all such destructive tests, the controller driving the FET failed too, sometimes quietly, and sometimes quite spectacularly. But either way, this was perfectly OK as per UL, since 'safety' was the only concern here, and this should never have been compromised. But in fact, in one case safety did get affected! In this case, the optocoupler, which was as usual connected to the controller for regulation purposes, cracked open. Now that was something unacceptable to UL, since it meant that the 'sacred' primary to secondary insulation barrier (inside the opto) had somehow gotten breached. That could conceivably lead to a hazardous voltage level from the mains line input (primary side) reaching a user who may have been in physical contact with the system (secondary side) at that very moment. Of course, thereafter, the input fuse would also blow up, disabling the entire system. But a fuse can never be relied upon to blow up fast enough to prevent electrocution, its main use is only in preventing a fire. This is the rapid chain of events that had apparently occurred: 1. The FET blew up and its drain and source shorted together. 2. The resulting high current ripped through the current sense resistor in the source, causing this MOF (Metal Oxide Film) resistor to fail open. 3. The inductor current coming in through the drain, still needing a path to freewheel through, diverted into the gate, raising its voltage and then entering the controller IC. 4. The controller IC then failed and the high voltage/current damaged several components connected to the pins of the IC, including the optocoupler! 5. The optocoupler cracked, and its safety barrier was breached. 6. Finally, the fuse blew (but too late!). 7. About half an hour later, the 'prime culprit' (one sleepy and hapless power supply design engineer somewhere out there) receives a midnight call from his fulminating boss. Surely the topic this time is not any upcoming promotion. Now, had we pored over some older power supply designs we may have seen that a transient voltage suppressor ('TVS') was often 'mysteriously' placed across the current sense resistor. In fact, its purpose was to circumvent this very chain of events. It takes us from the end of Step 2 straight to step 6. A TVS is basically just a rugged zener diode, and one that is designed to always fail in a shorted condition. So when the MOF resistor fails in Step 2, the resulting rising voltage would cause the TVS to almost simultaneously fail too, thus maintaining galvanic continuity for the current to keep flowing from drain to source to ground, till the fuse interrupts. So in this case, the current wouldn't need to divert into the gate (and the IC) as happened in Step 3. But we note that a TVS is a fairly expensive solution. So in Singapore, we decided to try a zener between gate and ground. In this location, the zener also always fails in a shorted condition. It thus protects the controller IC and all its associated components (including the opto), till the fuse interrupts. During debugging stages, or in initial prototyping, a gate-source zener comes in real handy too. It not only saves a lot of soldering/desoldering, but it dramatically extends the life of the constantly reworked board. Because though the FET fails, the controller IC and all its associated components always survive. So even after an otherwise 'impressive' blow-up, we usually just need to replace the FET, the current sense resistor, the zener, the pull-down gate resistor, and input fuse, to be up and running again in half an hour. And the skeptics: some are still convinced that the small anode-cathode zener capacitance can combine with the input capacitance of the FET and the lead and trace inductances to form a high-Q pi type of tank circuit (C-L-C). So they recommend a small resistor of about 10 ohms placed between the zener and the gate lead, to damp out any oscillations. Yes, inarguably, the zener must be very close to the FET, but about the oscillations?!! Well, one prominent FET manufacturer earlier was quite sure that this doomsday scenario could really happen, and had even stated as much in a certain Application Note (though this section was later removed). On further inquiries (from me in particular) they backed off, and in fact provided fresh data to actually disprove their own earlier assertion. So ultimately, privately they blamed it on one lone engineer of theirs, who didn't quite 'follow the book' when he reported he saw 'oscillations.' Probably a bad scope probe. We will never know. Better Do the Math: Ignore Transfer Functions at Your Own Peril It seems that there must be at least two distinct groups of people working in power, writes our power supply guru. One group consists of academicians who invoke integral calculus equations to describe a buck regulator. Another group of power supply professionals may wonder if this is going to really help them design better products. SMPS-guru says the math CAN translate into a better product, not just some yellowing seminar material fighting for immortality on a dusty shelf. It seems that there must be at least two distinct groups of people working in power. One consists of academicians who won't hesitate to invoke integral calculus to derive the dc transfer function of a buck topology (and then write textbooks filled with equations). Another group is practicing power supply professionals, many of whom tend to believe that anything even remotely abstract is not going to really help them design better products. I personally feel that there is a valuable middle ground available to all of us here. By presenting examples of interesting "transfer function interactions," I am hoping to show that it does actually help significantly if engineers try to think in a relatively abstract manner, and it can translate into a better product, not just some yellowing seminar material fighting for immortality on a dusty shelf. The dc transfer function of a topology is simply the expression connecting the input and output voltages. Most engineers realize that it follows directly from the fact that we have a voltseconds law in existence, which must be diligently upheld by the concerned inductor of any viable topology. 'Viable' implies that the topology (discovered or yet-to-be) can exist indefinitely in a steady and stable state. If not, we will certainly hear about it from the switch. Now consider the equation for the output of a buck-boost in discontinuous conduction mode ('DCM') VO = [(D2 · V^2_IN · 10^6) / (2 · IO · L · f)] Volts ... ... where VO is the output voltage of the buck-boost, L is in µH, and f is in Hz. This therefore has the following dependency VO prop. to D^2 · V^2_IN Now consider the dependency of a buck converter in continuous conduction mode ('CCM'): D prop. to 1/VIN So the point here is as follows: if we have a composite topology in which the duty cycle of a buck in CCM is used to drive a buck-boost in DCM, we can get the dependency on Vin above to cancel out completely as follows: VO prop. to 1 / V^2_ in · V^2_in = constant What does this tell us? If the output of the buck-boost is independent of the input voltage, clearly we must have inherent line regulation. And it’s for free! In practice, if we have a PWM controlled master buck stage, whose switching waveform is used to drive a slave buck-boost stage which has no independent PWM (just the switch being toggled), then we know that the output of the buck is certainly well-regulated (because we have a PWM and independent regulation loop), but the output of the buck-boost is also partially regulated with respect to line variations. We have no load regulation, but if the load of the buck-boost is fairly constant, we may not need it either. Or we can clamp the output of the buck-boost with a zener to give it constant load characteristics. Do note that this isn't bad considering we have only one PWM control! We can also use the fact that the output voltage of a discontinuous mode converter at a given duty cycle depends on its inductance. So we can 'tune' the slave buck-boost to have the required output level (at its expected maximum load current) by a careful choice of inductance. Within a valid range, this technique provides completely adjustable auxiliary output voltages, something we cannot normally expect from composite topologies based only on continuous conduction modes. Note that the zener on the output of this slave converter is almost completely nonconducting when the slave converter is working at its designed (maximum) load. The efficiency is therefore as high as we normally expect from any conventional switching power converter. However, if the load on the slave decreases, the zener comes into play and starts automatically shunting the balance of the current away. It’s then behaving as a conventional shunt regulator. Therefore load regulation, which is taken for granted when dealing with single or multi-CCM stages, is not 'automatic' here. It’s being 'enforced' by the zener, but luckily, if the inductance has been chosen correctly, this needs to happen only at less than maximum loads. So how did we manage to achieve automatic line regulation? As the input voltage increases, the feedback loop of the regulated buck converter commands its duty cycle to decrease to maintain output regulation. It just so happens that this decrease in duty cycle is exactly what was required by the discontinuous mode buck-boost to 'regulate' its own output almost perfectly. Have you also ever wondered why the number of turns on a single-ended forward converter transformer (not its output choke) can be calculated either at the high input voltage extreme or the low input voltage, or in fact at any input voltage? Here we have a transformer operating in DCM, but with a duty cycle dictated by a CCM equation (since it’s coming from the output choke). Only then do we get a surprising transfer function coincidence: that when the switch is ON, the product of the applied voltage across the transformer and its duration (the voltseconds) turns out to be a constant, irrespective of the input voltage. Therefore any input voltage will give us the same number of required primary turns. Now I need to transfer some of my functioning into other worldly interactions. Aluminum Cap Multipliers--Why We Can't Have Them and Eat Them Too With virtually the highest available CV (capacitance times voltage) capability, accompanied by the lowest cost, aluminum capacitors are still not even close to getting canned into history books, as some would think. Some of our younger engineers get rather charged up thinking about ceramic and modern polymer technologies, writes SMPS-guru. They should really be paying closer attention to aluminum electrolytics. With virtually the highest available CV (capacitance times voltage) capability, accompanied by the lowest cost, aluminum capacitors are still not even close to getting canned into history books, as some would think. Some of our younger engineers get rather charged up thinking about ceramic and modern polymer technologies, but they should really be paying closer attention to the viability and finer design aspects of the still undying aluminum electrolytic capacitor (hereafter called an 'elko'). So why not use an elko?? OK, it has a higher ESR. Granted! But let's not forget that 'all-ceramic' solutions can exhibit dangerous input oscillations, and it’s now actually being recommended that to damp out these oscillations we should put a high-ESR elko in parallel to the existing input ceramic cap. We may also require a higher ESR just to ensure stability when using voltage-mode control. To cut to the chase, let us therefore assume that we finally see the need to use an elko in a particular location. Now the main concern with such a component is its life expectancy. Eventually, the electrolyte inside will evaporate causing the capacitance to decrease, and beyond a certain level we would declare the capacitor 'dead' (worn out). We can clearly understand that a few factors will play key roles in this process: a) The hermeticity of the end seals of the capacitor. However, no joint is one hundred percent perfect, and so some evaporation will take place slowly over time. But we see the need to pick a vendor with a high (and consistent) quality. b) The surrounding temperature. The heat could come from nearby components or through internal heat dissipation. If we lower the temperature, the evaporation rate will decrease, and extend the life. We will see a little later how this leads to the published 'temperature multipliers.' c) The core temperature. We expect that there will be hot-spots inside the capacitor since we have less-than-perfect thermal conductivity inside it. As a worst-case, that is the temperature to consider when calculating life. In fact the entire life expectancy calculation is reduced to accurately predicting this core temperature (since we can't measure it). d) The ESR. This would certainly affect the internal heat dissipation, possibly raising the temperature and aiding the evaporation process. e) The frequency. Since ESR can be a function of frequency, the frequency will indirectly affect the life of the capacitor. We will see that this leads to the published 'frequency multipliers.' The most important datasheet parameter is the ripple current rating. This is typically stated in Amperes RMS at 120 Hz and 105 C. It essentially means that if the ambient temperature is at the maximum rating of 105 degrees C, we can pass a (low frequency) current waveform with the stated RMS, and in doing so we will get the stated life. The declared life figure is typically 2000 hours to 10,000 hours under these conditions. Yes there are lower grade 85 degrees C capacitors available, but they are rarely used, as they can hardly meet typical life requirements at high ambients. Let us now understand what a frequency multiplier tells us. The ESR of an elko is also usually stated at 120 Hz. The vendor may have directly provided a ripple current rating at 100 kHz in addition to the 120 Hz number. If not, he would certainly have provided 'frequency multipliers.' A typical frequency multiplier is 1.43 at 100 kHz. That means that if we are allowed 1 A ripple current at 120 Hz, then at 100 kHz we are allowed 1.43 A. This, by design, will produce the same heating (core temperature rise over ambient) as 1 A causes at 120 Hz. Therefore this is also equivalent to saying that the ESR at 100 kHz is related to the ESR at 120 Hz by the following equation: Thus the high-frequency ESR is about half the low-frequency ESR. Frequency multipliers should be used always, or we will overestimate the heating and underestimate the life, possibly forcing us to move to a larger cap size. Temperature multipliers we have to be more careful about. And we have to clearly understand what they really imply. The datasheet usually provides certain 'temperature multipliers' for the allowable ripple current. For example for the old but well-known LXF series from Chemicon, the numbers provided are 1. At 65 degrees C the temperature multiplier is 2.23. 2. At 85 degrees C the temperature multiplier is 1.73. 3. At 10 degrees C the temperature multiplier is 1. This means that if For example the rated ripple current is 1 A (at a maximum rated ambient of 105 degrees C), then we can pass 1.73 A at an ambient of 85 degrees C, and 2.23 A at an ambient of 65 degrees C. But in doing so, the core temperature will remain the same. So what is the actual story the temperature multipliers are telling us? The amount of heating and the core temperature rise are proportional to I^2 RMS, so if we assume that in every case the final core temperature was the same, that is, TCORE, then comparing the 105 degrees C ambient case with that at 85 degrees C: We can thus solve for TCORE to get... . This says that if we pass 1.73 A at 85 degrees C, or 1 A at 105 degrees C, the core temperature will be 115 degrees C in either case. In fact, for most 105 degrees C rated capacitors, we will have roughly 5 degrees C differential from ambient to the outer can and then another 5 degrees C from the can to the innards (the core), giving us a total of 10 degrees C from ambient to core. Let us check our reasoning by confirming the 65 degrees C multiplier ... So the multiplier must be 50.5 = 2.236, which agrees with the published datasheet value. Therefore we see that from the vendor's published ripple current temperature multipliers, we can easily deduce his designed-in maximum core temperature. The problem with this is that if the core temperature is at its maximum rated 115 degrees C, the life would always just be the declared 2000 hours or so. But that is hardly enough to get us through even one quarter of a year. We usually need at least about 44,000 hours (5 years) of life expectancy from all elkos used in a typical commercial power supply. How do we get there? We do that by reducing the core temperature thereby slowing the evaporation rate of the electrolyte. Does this imply we should not be using temperature multipliers to increase the current? There is actually another complication. It has been determined that not only is the absolute value of the core temperature important, but the differential from can to core is critical too. So if we increase the differential beyond the designed-in 5 degrees C, the life can deteriorate severely, even if the can is held at a lower temperature. But the designed-in differential of 5 degrees C occurs ONLY when we pass the maximum specified ripple current (no temperature multipliers applied), and that is irrespective of the ambient. Which means that as a matter of fact we cannot use any temperature multipliers at all. So, if the cap is rated to pass 1 A at 105 degrees C, then even at an ambient of say 65 degrees C, we are allowed to pass only 1 A, NOT 2.23 A. When the differential is decidedly kept equal to or less than the designed-in value, the life of the elko is then determined by the familiar doubling rule - for every 10 degrees C fall in core temperature (from its maximum rated), the life doubles. That is how we can finally get the required 44 khours. For example if the core is correctly estimated to be at 65 degrees C, then the calculated life of a 2000 hour capacitor is actually 2000 × 2 × 2 × 2 × 2 × 2 = 64 khours. But we do see that we can't have our cake and eat it too. We can increase the ripple current (but not the life) by applying the temperature multipliers OR we can increase the life (but not the ripple current) by not applying these multipliers. We just can't have it both ways! Elkos give us lots of benefits as it is, and we just shouldn't be asking for any more. Limit Your Peak Current, Not Your Reliability Pop. Pop. Pop. Pop. It's not the Fourth of July. It could be your own dc-dc design blowing up, worries our power supply expert, SMPS-guru. You do want to check out your design under a variety of adverse conditions, he suggests. Fault management is the key to designing power supplies that last. Now that you finally got your dc-dc converter working, is it really time to start popping the champagne? Shouldn't you at least wait to see whether it even survives the very first abnormal condition that comes its way? You don't really want to be the one to have to decipher (in your rather understandably hazy and exulted condition) whether that second pop came from the adjoining bottle or from your very own power supply. Fault management is the key to designing power supplies that last. Unfortunately, all this also has the immediately sobering potential to completely unmask the full extent of your design capabilities! Therefore, ensure that your current limiting is up to the task before you begin to celebrate. In a typical high-power off-line supply, fault management requires a clear understanding of the required shutdown and subsequent recovery sequencing of the various constituent stages: the power factor correction stage, the auxiliary (house-keeping) power supply, and the power trains. This is complex for sure. Therefore, in single-chip converters, we tend to think that the task of surviving abnormal conditions is trivial. But not so fast buster! A great deal depends on how quickly the current limiting acts. Also, whether it’s set correctly to start with. And whether it can even do its expected job. (For the latter aspect, we will delve into the subtleties of 'frequency foldback' in our next column. Here we first do all the necessary spadework.) In the high-voltage off-line power industry, the underlying design philosophy is to size the transformer as per the current limit. Which means that the transformer should not saturate even if the current hits the limit, as it usually will during any normal power-up or under shorts or overloads. Of course it’s always good to have the flexibility to set the current limit 'correctly'- to be just able to meet the required holdup time, step load capability, or any specified transient peak load requirement (as for disk drive motors, incandescent lamp loads, and so on). So though the thickness of the copper windings is certainly determined only by the continuous operating current (long-term heating effects), the actual physical size of the magnetic core must be set strictly according to the current limit alone. And this may or may not be related to the continuous operating current, as could easily happen if we use some popular integrated switcher families which provide only a discrete range of built-in fixed current limits. Implicit in this design strategy is the realistic realization that we just cannot set a given current limit, and expect it to be enforced fast enough to be able to save the switch if the transformer starts saturating, even momentarily. While this was blatantly obvious for bipolar transistors in the past, though the situation has improved with the advent of FETs, it’s not enough to have changed this basic design philosophy. At least not for high-voltage applications. The design philosophy prevalent within the low-voltage dc-dc semiconductor industry is so vastly different from that of the off-line power industry, that trans-migratory power engineers (nomads like me in an eternal search for a meaningful home) have a hard time reconciling initially. Here too, we can have families of integrated switchers with fixed current limits, but we almost invariably end up totally ignoring the current limit (just so long as it’s high enough to guarantee the desired output power). So we size the inductor according to the continuous operating load current - no more, no less. For example we may use a switcher with a 5 A current limit for a 2 A application, and use only an inductor rated for 2 A. We could also use the same switcher for a 4 A application and we would then use a 4 A inductor. Here we are assuming that since the switch is obviously OK with a current of 5 A, then even if we use a 2 A inductor, and it saturates momentarily, the current limit circuitry is capable of acting fast enough to immediately turn the transistor OFF the exact moment that it attempts to exceed 5 A. So the switch can never be destroyed, since its legal limit is assiduously enforceable. Now this scenario is clearly more likely to be true for FETs than bipolars, because the former have virtually no storage/delay times and can react almost immediately. But "almost" is not always good enough. Not in power. For example, if the input voltage is raised, the saturating inductor's current may ramp up so steeply, that even during the minimum ON time (minimum pulse width), the current may spike up high enough to damage the switch. In this case, we should ensure that the inductor is not saturating at the moment the current attempts to exceed the set current limit. That gives the circuitry enough time to safely turn the switch OFF. While testing and evaluating the LM2590HV to LM2593HV family of high-voltage devices we observed some failures if we used very small sized inductors when the input voltage was higher than 40 V. Thus our official recommendation in the datasheets for the inductor selection is somewhat of a cross between the two design philosophies talked about above - we have stated that if the input is less than 40 V, the inductor should be sized as per the continuous rated load current, but if the input exceeds 40 V, we should size the inductor as per the fixed current limit of the device (disregarding the load current totally). We should also keep in mind that the above mentioned devices are bipolar-based integrated switchers. We can expect the situation to be better if we use integrated devices which use FET switches. On the other hand, if we are using controllers, then even with FET switches we should be cautious, because the switching speeds and corresponding delays are likely to be worse than with integrated switchers. It all boils down to our ability to set the current limit accurately and to enforce it fast enough. It’s not a trivial proposition. The reader may wonder how we ensure rock-solid reliability for low-voltage applications if we disregard the current limit altogether, as we effectively seem to be doing above. Well in reality we don't, but this aspect is cleverly hidden from most users, though not deliberately so, and certainly not to their disadvantage! Most integrated switcher families are actually virtually 'bullet-proof.' And one of the key methods to ensure this is by providing a second level of current limit protection, usually not even mentioned in the datasheet, since it’s rarely encountered and almost completely transparent to the user. But this second limit is typically about 20 to 30 percent higher than the first (declared) current limit. If this is ever encountered, as with severely saturating inductors and high input voltages, the IC is designed to enter a foldback condition. As we said, more on this subtlety the next time!! Reliability Is No Flash in the Pan Don't be so quick to pop the champagne when your new power supply prototype seems to work, SMPS-guru wags a finger. Lest you want a lawsuit, ensuring reliability requires a disciplined effort around a second current limit. It's a long lonely trudge back to the drawing board, he says. That was some night of celebration! Now past the ebbing wave of our once-blissful incognizance, we are become increasingly aware that the fireworks display back there did not herald the onset of any new-found freedom - rather a lonely trudge back to the drawing board in the very near future, accompanied only by the growing realization that a) switching power conversion is not half as easy as it sounds, and b) reliability should never be considered to be a flash in the pan. In the previous month's column we revealed that many integrated switcher ICs are virtually indestructible by design. In that case, why even bother about knowing all about the peak currents? To answer this delicately and with a measure of natural human kindness, the second current limit not only helps make the IC 'bulletproof,' but also 'idiot-proof.' This second current limit, if present, is not even supposed to be encountered under normal operation, or even under "normal abnormal conditions!" That sounds oxymoronic, but in fact most of us practicing engineers would have to struggle extremely hard to even get the peak current to slip past the first current limit unnoticed, so as to trigger the IC into this last-ditch survival mode. But if that happens, unfortunately, now the problem is that the converter output just folds back (low output voltage at higher loads). This in turn is the result of the second level current limit comparator being designed to either cause a smooth, progressive reduction in the switching frequency ('frequency foldback'), or just skipping several on-pulses (the number of pulses skipped being roughly proportional to the amount by which the peak current is exceeding the second level threshold - an averaged sort of frequency foldback). But before looking further at frequency foldback, let us again beat upon some of the points from the previous month's column, and refine them further. We saw that for a low-voltage integrated switcher, we can for example use a "5 A device" for a 3 A load, and then its OK to use only a 3 A inductor. Note that we have been talking only about buck switchers so far. A "5 A" buck switcher is by definition meant for a maximum load current ('Io') of 5 A, and therefore its current limit ('Iclim') will usually always be internally set a little higher, maybe between 6 to 6.5 A. But this train of logic relies on a property that is specific only to the buck topology: its average inductor current equals its load current. We also recollect that the usual design procedure for selecting the inductance for any dc-dc topology is to set the peak inductor current about 20% higher than the average inductor current. We can show that this '20% inductor criterion' leads to an 'optimum' of sorts from the viewpoint of all the power components of the converter (for more details see application note AN-1197 at http://power.national.com). So for a buck, with a 5 A load current, we will typically have a peak inductor current of 5 × (1 + 0.2) = 6 A. But remember, this holds only for a buck! For 'non-buck' topologies we have to be careful because there the load current has no simple relationship to the average inductor current. And therefore nor to its peak or to the required current limit either. This means that if we come across a device declared to be say a "5 A buck-boost" (or boost) switcher IC, we should remember that this just means that 5 A is its set current limit, NOT its max load current. The max load for a non-buck topology depends on the input-output conditions of the particular application. For the boost and the buck-boost, the average inductor current is not the load current 'Io' but is Io divided by (1 - D), where D is the duty cycle. (See AN-1246 at http://power.national.com for more details). This leads to the following basic design rule for the two 'non-buck' topologies: the worst-case average (and peak) inductor current occurs at the lowest input voltage. That is thus the input end at which we must design or select our inductor. In contrast, for a buck, we always pick its inductance at the maximum input voltage of the application, because that is the end at which its peak current is the maximum. We need to refine the above numerical computations slightly and to also see the importance of tolerances in reliability and cost. We said that for a low-voltage 5 A buck we can pick a 3 A rated inductor if our max load current is 3 A. That is not completely accurate. Though the chosen inductor is allowed to have a 3 A continuous rating (based on the copper thickness and core loss), its peak or saturation rating (i.e. the current at which the core shouldn't saturate even momentarily) must be such that it can handle the peak current, which by design is typically about 20% higher than the average value, that is, 3 × 1.2 = 3.6 A. But we also know that if this happens to be a "high-voltage" application (defined here as an input greater than about 40 V) we may have to size our inductor according to the current limit, not the load current. That number is 5 A in this case. But very roughly so! Here we should actually check the IC datasheet to see the MAX value of the current limit range. For example, for a 5 A switcher the MIN value may be say 6 A (set high enough simply to guarantee full 5 A load capability with the usual 20% inductor design criterion mentioned above), but the MAX value of the current limit may be say 7 A over temperature and process variations, and depending upon how it may have been trimmed in production. So now, though the inductor needs to have a minimum continuous rating of only 3 A (for a load current of 3 A), the inductor must be able to handle peaks of 7 A! That primarily determines the size and cost of the inductor. Not the amount of copper. In fact, for a high voltage application, the load current is not really important anymore, because the weight of copper used doesn't really affect the inductor cost much, provided of course that the available winding window area is enough to accommodate the required number of turns, and so we are not being forced to pick a larger core size simply to accommodate the required windings, or because the overall core temperature is too high as a result of excessively thin wire gauge. We also now realize that all "5 A" switchers from different vendors are not necessarily the same! The spread/tolerance of the current limit is very important as it determines the size and cost of the inductor when dealing with high voltage ICs. The MIN value of the current limit is important because it determines the minimum guaranteed power output, and the MAX value of the current limit determines the size of the inductor. Therefore, some key manufacturers of high voltage integrated circuits pride themselves on how 'tight' their tolerance is on the set current limit. That is indeed admirable, but only provided we are comparing apples to apples; that is, comparing only high voltage integrated switcher families with fixed current limits from different vendors. This comparison makes no sense if we have a device (e.g., a controller) where we can set the current limit externally. In that case we can match the current limit much more accurately to the load current, and thus get the smallest possible core size. That helps reduce core size. (More on this aspect in the next month's column and how such vendors virtually trick us into 'thinking' that the core size has decreased.) For non-buck topologies, we now realize that say for a buck-boost application with an input of 15 V to 25 V and an output of 15 V output, the max duty cycle is 50% and this occurs at the minimum input of Vin = 15 V. So if the load current is 5 A, the average inductor current is 5/(1 - 0.5) = 10 A. With the 20% inductor criterion, the peak switch current will be 10 × 1.2 = 12 A. So the MIN of the current limit must be set higher than 12 A. And then depending on the available accuracy for current limit, the MAX may be as high as say 20 A. Clearly, a 5 A switcher is not going to suffice, nor an inductor rated only for 5 A! A related issue is the case when a buck IC is used in a so-called 'inverting configuration'. We should realize that in doing so actually the topology has in effect changed from a buck to a buck-boost. So now we just cannot get 5 A of load current from a declared '5 A' IC. How much load current is possible depends on the specific input-output conditions. So again, our peak current is not close to 5 A, nor should the inductor rating be "5 A". Or we will certainly be frozen into a July 4th timeframe forever. From an IC designer's point of view and even our applications level understanding, we must carefully recognize another basic problem with the very concept of current limit. Suppose we now have a very 'fast acting' current limit, and we also use 'blazingly fast' FETs (very low gate charge). Does that mean we are 100% protected? Not necessarily! What does the current limit comparator really do? All it can do is to command the duty cycle to reduce further when we hit the current limit. But it can't make the pulse width narrower than a certain minimum on-time. This small minimum pulse width of about 100-150 ns is usually required for the internal circuitry to be able to sense the current every cycle, and we also actually have to turn the switch ON every cycle for the purpose. In fact this minimum pulse width may need to be set even higher, say around 150-250 ns, especially if we are using controllers (as opposed to integrated switchers) since a 'good' controller IC must handle a relatively wide range of FET characteristics, and various possible PCB layouts and their corresponding trace delays and glitches. Current mode control may also be worse off in this regard, because of the need to incorporate a certain higher than usual minimum leading edge noise blanking time. Generally, high frequencies will aggravate the situation further, since the same minimum pulse width corresponds to a much higher minimum duty cycle at high frequencies. What this leads to is the very curious situation as indicated in Fgr. 2 (for a buck). Consider a 'hard' power-up, that is, a sudden application of input power, with a high dV/dt, as say with a banana plug slammed into the lab dc power supply. Initially, there is no output voltage rail present, so the current ramps up at the rate of Vin/L, eventually steadying to (Vin - Vo)/L. But during the off-time, at initial power-up, the ramp-down rate is much smaller, as it depends basically only on the diode voltage drop of 0.5 Volts or so. So every cycle, the net current rises just a little higher, irrespective of any current limit. This is a clear case of current staircasing. Over several cycles, depending on the amount of output capacitance and the input dV/dt, the inrush current may go up to very high and almost unpredictable levels. Even 'soft-start,' if available, may serve absolutely no purpose at all, at least not in controlling the inrush current. The situation actually gets worse with a 'good' diode, that is, one where the diode voltage drop is less, because it’s this diode drop that stands almost alone in trying to get the current to ramp down. The same thing happens if we short the output! One solution to this problem is to reduce the frequency (or just omit on-pulses as shown in the lower diagram of Fgr. 2). This effectively increases the off-time and reduces the minimum duty cycle, and thus gives enough time for the current to ramp down. See the datasheet for LM1572 (at http://power.national.com) for a deeper explanation of such a practical frequency foldback scheme. But note that if too much off-time is available (an excessive amount of frequency foldback), the average current may not be able to rise high enough to meet even the initial load requirement under startup. That could well lead to a scenario that is rather uncomfortably well known in the semiconductor industry - that of an IC which has a declared and mysterious "startup problem" under certain types of loads. In general, we have to be very careful in implementing any type of foldback scheme. Foldback is a two-edged sword. It might help control responses to abnormal conditions, but may also end up encroaching on normal responses. == AVERAGE---AVERAGE Slope = -VD/L Slope = VIN/L Slope = -VD/L Slope = VIN/L Minimum Pulse Width FREQUENCY FOLDBACK NO FREQUENCY FOLDBACK Fgr. 2: Frequency Foldback == Another method being used nowadays for synchronous buck ICs is to sense the current during the off-time (i.e. across the lower FET). Note that this allows us to skip on-pulses entirely and is in effect a frequency foldback of sorts. Though its main purpose in powering modern core processors is to be able to carry out a high-to-low conversion at high switching frequency. For example, from 20 V to 1 V at 1 MHz would require 1/20th of 1 µs, that is, an on-pulse no wider than 50 ns. That doesn't leave us much time to be able to sense current in the high-side FET. So the only option is to sense current in the low-side FET. On the face of it, low-side sensing should also help restrict the current under startup and overloads. But it has its own set of peak current and reliability problems, and these will form the subject of a column in the near future. |
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