Switching-Mode Power Supply (SMPS)--Input Capacitor and Stability Considerations in EMI Filters

• Is the DM Choke Saturating?
• Practical Line Filters in DC-DC Converter Modules

There are certain things we may do unintentionally at the input of the converter that can have a major impact on the performance of the EMI filter, and also the converter itself. If we don't know the rules of the game, we can end up saturating our filter chokes and even inducing instability.

Is the DM Choke Saturating?

Part of the designer's average "EMI troubleshooting day" may involve taking a core from the shelf and placing some turns on it. But the temptation of winding a few more turns (to increase the inductance) may just do it - the core could start saturating, rendering it less and less effective. But how could we have known that? The simplest equation to check if a core is saturating or not is

B = (LI / NAe) teslas

where L is the measured inductance in H, N the number of turns, and Ae is the effective area of the core in m2. Note that Ae is simply the normal geometric cross-sectional area of the core. If it’s an E core, we would take the area of the center limb (or twice the area of each side limb, whichever is smaller, though usually, either way we get the same result). So if we plug in the peak current we can calculate the peak B-field in the choke. If we know the material of the core, we probably already know its saturation flux density BSAT. Then we can easily check if the core is saturating or not. Note that BSAT for powdered irons is usually around 10,000 gauss (1000 mT or 1 T) and for ferrites it’s 3000 gauss (300 mT, or 0.3 T).

But what is the peak current? This is the term that is usually completely underestimated by most designers, and that is why they often don't realize that their DM choke is ineffective because it’s saturating.

The temptation to wind a few more turns on the DM choke (if present of course) in an effort to raise its inductance may just produce enough ampere-turns to saturate it. What happens after that depends a lot on the material itself. Powdered iron may be more forgiving up to a point, but then it also has lower initial permeability to start with. Ferrites can saturate comparatively more sharply (though we know that air helps soften that - either in the form of an air gap, or distributed, as in powdered iron). Of course if the DM choke is just the leakage inductance from the CM choke, then in effect it’s a completely air-cored coil anyway, and we don't have to worry about it saturating.

So in DM chokes, the major concern is core saturation. But in CM chokes, underestimating the current will make it run excessively hot, due to higher copper losses.

In a typical off-line input stage, with no Power Factor Correction ('PFC') stage present, the input bridge conducts only for part of every ac half-cycle as seen from Fig. 1.

The input (bulk) capacitor discharges slowly, during the remaining time, at a rate that depends on the power it’s delivering to the converter - which except for the small loss in the filter itself, is essentially equal to the input power, that is, P_IN = P_OUT/?, where PIN is the power being drawn from the supply lines, for given output power POUT at a certain efficiency, ?. If we put larger and larger bulk capacitance we can end up with extremely high peak and RMS currents through the input bridge and the filter chokes (along with a lot of low-frequency harmonic content that is regulated separately by line harmonic standards - i.e. PFC-related). The higher currents are attributable to the fact that the bridge conduction time becomes shorter as we increase the bulk capacitance. And since a certain amount of average input power is being constantly demanded by the converter, the current "bursts" through the diodes must increase in amplitude, so as to compensate for the shorter gating interval.

Knowledge of the input RMS current is necessary to correctly estimate the copper losses in both the CM and DM chokes, whereas knowledge of the peak current is necessary to correctly estimate the DM core volume (its energy handling capability). In a CM choke, the input ac line current effectively cancels out, so its saturation is usually not considered either a possibility or a concern. That means it’s "chopped" out of a vertically offset sine wave of that time period.

The shape of the input current into the power supply is usually described as a 'haversine'- which is simply a sine waveform offset on its vertical axis so as to make the minima of the curve coincide with the horizontal axis (t = 0). The current waveform shown in Fig. 1 is thus a haversine - with a time period equal to the diode conduction time (during which it occurs). That means it’s "chopped" out of a vertically offset sine wave of that time period.

The following equations can be derived.

The time for which each diode conducts is:

tC = cos-1 [A] 2 × p × f LINE seconds

Fig. 1: The Input Current Waveshape Analyzed.

[...]

C is in Farads above.

The RMS and average values of the current waveform (calculated only over the diode conduction time) are, respectively, ... where the peak of the current is

I_PEAK = 2 × I_AVG

We have to average the RMS and average values over the full ac cycle, as shown in the following example.

Example: A power supply delivering 5 A@14 A at 70% efficiency has a 330 µF input capacitor. What are the RMS and peak input currents at 265 VAC/50 Hz?

P_IN = 5 × 14 / 0.7 = 100 W

So A = 0.978, and tC = 0.67 ms. We calculate I_AVG = 4.05 A, I_PEAK = 8.1 A, I_RMS = 8.1 × 0.612 = 5A.

We have also provided a graphical method in Fig. 1 - for any general case (at a line voltage of 265 V-ac). In our case, the selected input capacitance per (input) Watt is 330/100 = 3.3 µF/W. We locate this value on the horizontal axis, and then we can see that this gives us about 0.05 A for the RMS current on the vertical axis. But the vertical axis is the current per Watt of input power. So for our case, the RMS current is 100 × 0.05 = 5 A. This agrees with our numerical calculation above.

Since we have two conduction intervals per ac cycle time period, the input average and RMS currents, now calculated over the whole cycle, are (with T = 1/fLINE) ...

Therefore, we have to ensure that our DM choke does not saturate with a peak instantaneous current of 8 A. Both the CM and DM chokes must have copper thick enough to handle 1.3 A RMS.

If we are dealing with a wide-input (universal) off-line power supply, we should check all the currents at low line too! At low line, despite the fact that the conduction time increases significantly, the required average dc input current is much higher too. So the peak/RMS currents will generally tend to increase, not decrease, as we lower the line voltage. If we assume efficiency is unchanged in going from high line to low line (i.e. PIN is a constant), then a detailed calculation based on the equations presented above reveals that the RMS, peak, and average currents increase by almost 4% exactly, in going from 265 V-ac to 90 V-ac (for 3 µF/W). Not much of an increase really! So Fig. 1 should suffice. Or we can do a detailed calculation.

Note that if we had PFC, then at 265 V-ac input, we would get an RMS current of only ...

The peak is also less ...

But note that, if this is a universal-input power supply, we again need to check the currents at low line too, and rate the chokes according to the worst case. In this case (with PFC), we see that at 90 V-ac, all the currents increase almost three times over their values at 265 V-ac (again assuming efficiency is unchanged in going from high line to low line).

However, it’s nevertheless clear that introducing power factor correction in off-line power supplies always leads to much smaller EMI filter chokes.

Tip: In a power supply without PFC, if we are trying to measure the bridge conduction time with an oscilloscope, we should ensure that the input to the power supply is not from a variac. An electronic programmable ac source is preferable, because the variac tends to appear inductive, and keeps trying to push its residual energy through the bridge for just a little longer. This increases the conduction time, and makes the peak current significantly lower than if the power supply is powered off the wall.

Practical Line Filters in DC-DC Converter Modules

Fig. 2: Typical EMI Filter for DC-DC Modules (bricks)

See Fig. 2 for an example of how EMI suppression techniques are applied to dc-dc converters. We have shown an industry standard isolated "brick" (along with its external EMI filtering). The input to this particular module is a coarsely regulated '-48 V-dc' or '-60 V-dc' bus, forming part of a distributed power architecture for a data/telecom network.

Its output is isolated and regulated (e.g. 3.3 V/50 A or 12 V/10 A etc). The -48 V-dc input is usually derived from an off-line telecom power supply (called a "rectifier").

Notice how the traces are laid out in the module's external EMI filter as illustrated in Fig. 2. Note, in particular, the placement of the Y-caps. We should also keep in mind that one of the most effective methods of suppressing EMI, especially in board mounted dc-dc converters, is a good ground plane. On a multilayer board, best results are usually obtained by having this plane be the internal layer just below the top (power) component side. Up to 20 dB reduction in noise is possible. The "input instability" issue, as indicated in Fig. 2, is discussed next.

Note: As per the usual safety regulations, voltages below 60 V-dc generally are not considered hazardous and therefore are not subject to the isolation/earthing requirements described earlier. But above 60 V we generally would need reinforced installation. However, in Europe, more recent definitions have evolved concerning 'Telecommunications Network Voltage' (TNV) circuits, which by their very nature are not accessible to humans in general. So for example, above 60 V-dc and below 120 V-dc we have what is called a 'TNV-2 circuit.' Though this requires insulation, it need not be of the reinforced/double insulation category. So in general, the Y-caps shown in Fig. 2 can be standard 2 kV rated components. However, if the preceding "rectifier" has reinforced isolation between its own output and the ac mains, then the Y-caps in the module can be just regular 100 V capacitors. Note also, that the Y-caps in a dc-dc converter are between two dc levels, so we can forget about ac ground leakage currents and their related safety issues as previously discussed. This gives us the flexibility of choosing large-capacitance Y-caps.

Note: For protection against ESD (electrostatic discharge) upsets, 0.01 µF caps between the terminal block contacts and earth are often also included. These are essentially Y-caps. But note that there have been cases, particularly when these caps were ordinary 50 V multilayer ceramic ("MLCs"), that they got destroyed during the course of an ESD test - simply because they got charged up to excessive voltages! Therefore, these capacitors, and any other Y-caps present, must be evaluated under such abnormal but likely disturbances too. Eventually, we may need to increase the capacitance and/or the voltage rating and/or size of the caps just to protect them from/against over-charging.

Since about 1971 the phenomena of 'input oscillations' or 'input instability' has received quite a lot of attention. It has been shown that instability can occur if the output impedance of the filter is not within a certain "safe" window, as related to the input impedance of the converter (we are talking about the impedances presented to the power flow now - not the CM or DM noise). So, with the modern trend of low-impedance "all-ceramic" solutions in dc-dc converters, the possibility of this particular type of instability is becoming more and more real.

One of the easiest ways to see the impact of the negative input impedance of a typical converter is to set it up with only ceramic input capacitors (about 10 µF or less) - and then do a "hard power-up." In this type of power-up test, the dV/dt of the applied input is kept intentionally very high. On the bench, this can be done by simply slamming the banana plug from the input of the converter into the output terminals of a (low-impedance/high-current) lab dc power supply. Then, if we monitor the input (supply) pin of the converter with a digital oscilloscope (triggered correctly, and in one-shot acquisition mode), we will see an initial overshoot - that can be as high as 1.5 to 2.5 times the supposed dc voltage level (as set on the lab supply). Note that if the input capacitance is large enough (beyond a certain value), the dV/dt (and overshoot) gets automatically reduced, due to the higher charging current required for this input capacitor. On the other hand, if the ceramic capacitor is replaced by an aluminum electrolytic (even one with a lower capacitance), the overshoot is dramatically reduced. Tantalum capacitors also produce overshoots under hard power-up, but these are less pronounced than with ceramic.

Note: We should remember that in any case, it's never a very good idea to use tantalums at the input of any converter - due to tantalum's inherent surge current limitations. However, if for some reason, tantalums must be used at the input (in any topology), or at the outputs (for a boost or buck-boost), we must ensure that they are 100% surge-tested by their vendors. And even for such surge-tested tantalum capacitors, it’s recommended that the maximum voltage applied across them in our application be less than half their voltage rating - that is, a voltage derating of 50%.

We see that it’s possible to damage a dc-dc converter, which uses only small-value ceramic capacitors at its input - more so when we already happen to be operating rather close to its maximum input voltage rating.

The designer should note that in Fig. 2, we have placed an electrolytic capacitor in parallel to the ceramic input capacitors - for the purpose of damping out "input instability." This needs further explaining. To understand the underlying causes associated with this phenomena, we need to start with the well-known buck converter equations and see what happens if we (hypothetically) "jiggle" the duty cycle, just a little bit, around its steady state value. Note that in a practical situation, this could happen very easily under normal line or load transients. Therefore, expressing the input voltage and the input current as a function of duty cycle:

V_IN(D) = VO / D

dIIN = IOdD

Dividing these two equations we get (for a buck converter)

This is the incremental resistance at the input. Let us call this "RIN." So for a buck converter, its incremental resistance in ohms is ...

R_IN =-RL / D2

Here RL is the load resistance (ohms), and is assumed constant. Note that both the input voltage and the input current always have positive values in a (positive-to-positive) buck converter. Therefore the ratio VIN/IIN is also certainly a positive quantity. It's only their relative change that is in opposite directions - hence the minus sign in the preceding equation.

Another way to look at it’s as follows. For a given output power PO, if the input voltage increases slightly, then the input current must decrease. That's because PO (and therefore roughly PIN too) must remain constant.

VO × IO = PO ˜ VIN × IIN

This is clearly true for any topology. We can therefore work out the (negative) incremental input resistance for the other topologies in a similar manner.

Example: What is the input resistance of a 3.3 V/50 V brick, with an input range of 36-75 V? Output power is 3.3 × 50 = 165 W. RL is 3.3/50 = 0.066 ?. Duty cycle is 0.092 at 36 V input. So the magnitude of RIN is 0.066 / (0.092) 2 = 7.8 ?. In terms of decibels this is 20 log (7.8) ~ = 18 dB?. A similar calculation at 75 V input gives 31 dB?. So the (magnitude of the negative incremental) impedance of the buck converter falls as the input voltage falls.

We will see that This means that this form of instability is more likely to occur at low input voltages.

What is it about the interaction of the impedances at the filter-converter interface that causes this instability? Let us see what is really happening as we jiggle the input to the filter (VIN).

See Fig. 3.

Fig. 3: Input Interaction and Two Possible Solutions to Increase Damping.

Here VINC is the voltage that appears at the terminals of the converter. The filter impedance and the converter impedance form a voltage divider.

V_INC = V_IN × Z_INPUT / (Z_INPUT + Z_SOURCE)

Looking at this equation, we ask - what happens if ZINPUT becomes negative? Numbers explain it best. Suppose ZINPUT =-30 Ohm, and ZSOURCE = 10 Ohm. Then VINC/VIN is equal to -30/(-30 + 10) =+1.5. This implies a 50% input overshoot. However things get uglier.

What if ZSOURCE = 40 Ohm instead of 10 Ohm?

Now VINC/VIN is equal to -30/(-30 + 40) =-3.

The sign looks odd! But let's not forget that we are actually talking of incremental impedances (the number crunching here is actually very simplified). So the sign of VINC is not really negative, but its change is.

What is being indicated is that if we momentarily increase the applied input voltage (at the input of the filter), the input voltage at the converter end falls slightly (though momentarily).

The control loop of the converter will however "think" that the input has fallen rather than increased, so it will respond incorrectly to the change. And isn't that the usual recipe for output oscillations?!

Therefore, the most basic criterion for avoiding this type of instability is:

ZSOURCE < |ZINPUT|

Now, in reality, the input impedance of the converter is frequency-dependent (RIN was just the low-frequency value of ZINPUT). In the more detailed converter model, a parallel capacitance CIN (see Fig. 3) appears across the input of the converter, mainly due to the output filter components of the converter being reflected into the input. This causes the (real part of the) input impedance to be less and less negative as frequency increases.

In Fig. 4, we have shown a typical input impedance plot with respect to frequency.

Note that only the magnitude of the converter impedance has been displayed, primarily because the y-axis is in log scale, and we know that log scales cannot be negative.

ZSOURCE (the output impedance of the filter) is also changing with frequency. Looking into the output terminals of the filter (from converter) we see basically a simple parallel LC filter stage. Therefore ZSOURCE has the shape indicated in Fig. 4.

Fig. 4: Input Filter Interaction and Stability Criteria. Impedance (ohms); OSCILLATIONS!

The stability criterion therefore means that we are demanding that the output impedance of the filter must be always less than the input impedance of the converter for any frequency.

But what happens if the LC filter has insufficient damping and therefore has a resonance peak? This is the encircled problem area in Fig. 4, and we can see that in this region we are violating the basic stability criterion. This peak needs to be suppressed. Therefore, in addition to the basic stability criterion, a follow-up criterion must be added to ensure that at resonant frequency, the LC filter peak is properly damped out.

For damping, we could simply add some more resistance to the choke (DCR) as shown in Fig. 3. But that is not a very good idea since the entire operating current also passes through this choke, and the overall efficiency would suffer. Instead, it’s preferable to add a slight resistance (ESR) to the capacitor as also shown in Fig. 3. We know that any capacitor in steady state blocks any dc voltage completely. So the input capacitor sees only the ac component of the input current flowing into the switching mosfet. This therefore correspondingly reduces the dissipation required to achieve a given target of damping.

However, we also need to maintain good decoupling at the input of the converter (to keep its control sections from getting affected, as also to suppress EMI). Therefore the usual commercially implemented solution for such bricks is to place an additional high-ESR capacitor in parallel to the existing low-ESR decoupling capacitors. It can been shown that we need to meet the following conditions to make the system unconditionally stable (the first of these is essentially the basic criterion discussed previously):

ESR < |RIN| ESR > L / CBULK × |RIN| CBULK » CINPUT

... where CINPUT is total capacitance at the input terminals of the converter (including CIN, ceramic capacitors, any X-caps, supply decoupling caps, and so on). CIN is typically a few µF, but without elaborate modeling of the converter, or some type of measurement, its value may be unknown to most designers. But generally speaking, if CBULK is chosen to be much larger, it effectively "swamps" out the effect of CIN, and so the system is stable anyway (the thumb rule is that CBULK should be four to five times the total effective low-ESR input capacitance physically present at the input to the converter, that is, before CBULK was added).