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1. INTRODUCTION
In the flyback converter, the primary inductance of the transformer (more correctly a multiple-winding inductor) is generally much lower than the inductance of its counter part in the forward converter. Hence, the rate of change of current during the primary conduction phase (the "on" period) is large, giving a large triangular shape to the primary current pulse. This triangular waveform is ideal for the application of current mode control, providing good noise immunity and well-defined switching levels to the current comparator.
With current-mode control there are two control loops in operation. The first, fast-acting inside loop controls the peak primary current, while the second, much slower outside loop adjusts the current control loop to define the output voltage. The overall effect of these two control loops is that the power supply responds as a voltage-controlled current source.
There are a number of advantages to be gained from current-mode control. First of all, the system responds as if the primary is a high-impedance current source and the effective inductance of the converter transformer is removed from the output filter equivalent circuit for small signal changes. This results in a simple first-order transfer function.
Hence the control circuit may have a good high-frequency response, improving the input transient performance. Line ripple rejection and loop stability are improved. A second major advantage is that primary current limiting is automatically provided without additional components.
2. POWER LIMITING AND CURRENT-MODE CONTROL AS APPLIED TO THE SELF-OSCILLATING FLYBACK CONVERTER
The self-oscillating complete energy transfer flyback converter responds particularly well to the application of current-mode control. This will be explained by reference to the circuit shown in FIG. 4.
The voltage across R4 (which sets the maximum collector current) cannot exceed 0.6 V under any conditions, because at this point Q2 will turn on, turning off the power device Q1. This will occur irrespective of the condition of the voltage control circuit, because the control circuit cannot change the voltage at the base of Q2 negatively. Consequently, the peak input current is defined by R4 and Q2 Vbe and cannot be exceeded. Thus R4 and Q2 provide automatic primary power limiting. The action of the remainder of the control circuit can only reduce the limit still further.
Although a very simple circuit is used, the power limiting action is excellent. The "on" period is terminated when the primary current has reached a defined peak level on a pulse by-pulse basis. This current-defining loop also sets a maximum limit on the transmitted power, 1/2 L_p I^2 _p f .
It should be noted that because the limiting action is a constant power limit, as the output voltage goes toward zero under overload conditions, the output current will increase. If this is unacceptable, then additional circuitry will be required to reduce the power limit as the load goes toward short-circuit, or to turn the supply off for overload conditions.
The second, much slower voltage control loop (R11, R12, V1, OC1a, and OC1b) responds to output voltage changes and adjusts the bias on Q2 so as to reduce the peak value of primary current required to turn Q2 on. This level is adjusted in response to the voltage control circuit to maintain the output voltage constant.
3. VOLTAGE CONTROL LOOP
Figure 1 shows the collector and emitter current waveforms of Q1 under steady-state voltage-controlled conditions. The emitter current waveform shows a DC offset as a result of the base drive current component Ib. An analogue voltage of the emitter current will be developed across R4. The voltage across R5 (VR5) shows the effect of the snubber current in R5 imposed on the voltage across R4, resulting in a rapid increase in voltage toward the end of the conduction period. The voltage waveform on Q2 shows the DC bias introduced by the control current from OC1b and R6 developed across R3 and imposed on the voltage waveform of R5.
When Q1 turns on, current will build up in the primary of the transformer, as shown in FIG. 1. A "sawtooth" voltage waveform will be developed across R4. This waveform will be applied to the base of Q2 via R5 and R3. A control current flowing in R6 and OC1 will bias the base of Q2 more positive, and the "on" pulse will be terminated when the volt age on the base of Q2 reaches 0.6 V. This turns Q2 on and Q1 off.
As soon as Q1 starts to turn off, the voltage on its collector will rise, and a current will flow in the snubber components D2, C5, and R5, generating a further increase in the voltage across R5 because R5 has a higher resistance than R4. This increase is applied to the base of Q2, providing regenerative turn-on action of Q2 and hence turn-off of Q1.
If the optocoupler OC1b is not conducting, Q2 will still turn on when the voltage across R4 has reached 0.6 V, removing the base drive from the main transistor Q1 and turning it off. Consequently, irrespective of the state of the control circuit, the maximum primary current is defined without the need for further current limiting circuits.
However, the shunt regulator U1 will conduct when the required output voltage of 12V is obtained, driving current through the optocoupler diode OC1a. In response to the optodiode current, the optotransistor OC1b will conduct, driving current into the resistor network R3, R5, and R4. The current from OC1b will add a fixed positive bias to the triangular waveform developed across R4 by the emitter current. Consequently, Q2 will turn off with a lower current amplitude in R4. The optotransistor OC1b can be considered a constant-current (high-impedance) source. Hence it will not interfere with the shape of the triangular waveform apart from adding the DC bias. The loop stabilizing components R10 and C7 make the response of the voltage control loop relatively slow compared with the current control loop.
FIG. 1 Current and voltage waveforms of self-oscillating converter.
So long as the required output power is less than the limiting value, the voltage control loop will adjust the bias on the base of Q2 so as to maintain the output voltage constant.
Resistor R6 provides a fixed offset bias to Q2 for final adjustment of the power limiting value. It also reduces the peak current when the input voltage is increased, because the auxiliary voltage on R6 tracks the input voltage. Finally, it also introduces some compensation in the variable-frequency system to improve input ripple rejection.
4. INPUT RIPPLE REJECTION
For constant-frequency, complete energy transfer (discontinuous-mode) flyback converters, the current-mode control also provides automatic input ripple rejection.
If the converter input voltage changes, the slope of the collector and hence the emitter current will also change. For example, if the collector input voltage starts to rise as a result of the normal rising edge of the input ripple voltage, then the slope of the collector and hence the emitter current will also increase. As a result, the peak current level will be reached in a shorter time and the "on" pulse width will be automatically reduced without the need for any control signal change. Since the peak primary current remains constant, the transferred power and the output voltage will also remain constant (irrespective of the input voltage changes). Consequently, without the need for any action from the control circuit, input transient voltage changes and ripple voltages are rejected from the output.
This effect may be further demonstrated by considering the input energy for each cycle.
As this unit operates in a complete energy transfer mode, the energy at the end of an "on" period will be:
1/2Lp I2p
where Lp = primary inductance
Ip = peak primary current
Since Lp and the peak current Ip remain constant, the transferred power is constant. This action is very fast, as it responds on a pulse-by-pulse basis, giving good input transient rejection.
A more rigorous examination reveals a degrading second-order effect in the variable frequency self-oscillating system, caused by an increase in the operating frequency as the input voltage rises. This frequency change reduces the ripple rejection. However, since the increase in frequency results in only a small increase in input power, the effect is quite small.
In the circuit shown in FIG. 6.4, the effect is compensated by an increase in the drive current component in R4 and an increase in the current in R6, caused by the change in the base drive and auxiliary voltages which track the input change. This compensation is optimized when the forced drive ratio is approximately 1:10.
5. USING FIELD-EFFECT TRANSISTORS IN VARIABLE-FREQUENCY FLYBACK CONVERTERS
At the time of writing, FETs were available with voltage ratings of up to typically 800 V; consequently, their use for flyback off-line converters was somewhat limited.
The maximum rectified DC header voltage Vcc for 220-V units, and also for dual input voltage units in which voltage doubler techniques are used, will be approximately 380 V DC. As the flyback voltage stress will normally be at least twice this value, the margin of safety when 800-V power FETs are used is hardly sufficient.
However, higher-voltage competitively priced FET devices are now freely available and there are significant advantages to be gained from using FETs and operating the flyback unit at higher frequency. This could result in a reduction in the size of the wound components and output capacitors. A more suitable circuit which reduces the voltage stress for lower-voltage power FETs is shown in FIG. 5.1.
6. QUIZ
1. Why do flyback converters lend themselves particularly well to current-mode control?
2. Why does current-mode control provide a simple first-order transfer function in the complete energy transfer mode?
3. Why is the input ripple rejection extremely good in the current-mode control topology?