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6. Testing, Bonding, and Packaging
After the preceding discussions of rather dramatic fabrication steps in monolithic circuit technology, the processes of attaching leads and packaging the devices could seem rather mundane. Such an impression would be far from accurate, however, since the techniques discussed in this section are crucial to the overall fabrication process. In fact, the handling and packaging of individual circuits can be the most critical steps of all from the viewpoints of cost and reliability. The individual IC chip must be connected properly to outside leads and packaged in a way that is convenient for use in a larger circuit or system. Since the devices are handled individually once they are separated from the wafer, bonding and packaging are expensive processes. Considerable work has been done to reduce the steps required in bonding. We shall discuss the most straightforward technique first, which involves bonding individual leads from the contact pads on the circuit to terminals in the package. Then we shall consider two important methods for making all bonds simultaneously. Finally, we shall discuss a few typical packaging methods for ICs.
6.1 Testing
After the wafer of monolithic circuits has been processed and the final metallization pattern defined, it is placed in a holder under a microscope and is aligned for testing by a multiple-point probe (FIG. 40). The probe contacts the various pads on an individual circuit, and a series of tests are made of the electrical properties of the device. The various tests are programmed to be made automatically in a very short time. These tests may take only milli seconds for a simple circuit, to several seconds for a complex ULSI chip. The information from these tests is fed into a computer, which compares the results with information stored in its memory, and a decision is made regarding the acceptability of the circuit. If there is some defect so that the circuit falls below specifications, the computer remembers that chip must be discarded. The probe automatically steps the prescribed distance to the next circuit on the wafer and repeats the process. After all of the circuits have been tested and the substandard ones noted, the wafer is removed from the testing machine, sawed between the circuits, and broken apart (FIG. 41). Then each die that passed the test is picked up and placed in the package. In the testing process, information from tests on each die can be stored to facilitate analysis of the rejected circuits or to evaluate the fabrication process for possible changes.
FIG. 40 Automated probing of devices: (a) high-speed testing of ICs
is done using probe cards having a rigidly fixed array of probes that corresponds
to the bond pad pattern on the IC to be tested. Many electrical signals
are provided or measured by the automated tester at the various pins. After
one chip is tested, the tester mechanically moves the wafer to the next
die location; (b) array of Al bond pads near the chip periphery, some showing
probe marks. The space between the arrays of bond pads is the "scribe
line" along which the wafer will be sawed into individual chips after
testing. (© 2004 Micron Technology, Inc.)
FIG. 41 Sawing of a wafer along scribe lines: After the wafer is tested,
the "known good dies" are "inked" or identified. The
wafer is then sawed into individual dies for subsequent packaging. (© 2004
Micron Technology, Inc.)
FIG. 42 Attachment of leads from the Al pads on the periphery of the
chip to posts on the package. (© 2004 Micron Technology, Inc.)
6.2 Wire bonding
The earliest method used for making contacts from the monolithic chip to the package was the bonding of fine Au wires. Later techniques expanded wire bonding to include Al wires and several types of bonding processes. Here we shall outline only a few of the most important aspects of wire bonding.
If the chip is to be wire bonded, it is first mounted solidly on a metal lead frame or on a metallized region in the package. In this process a thin layer of Au (perhaps combined with Ge or other elements to improve the metallurgy of the bond) is placed between the bottom of the chip and the substrate; heat and a slight scrubbing motion are applied, forming an alloyed bond which holds the chip firmly to the substrate. This process is called die bonding. Generally, die bonding is done by a robotic arm that picks up each die, orients it, and places it for bonding. Once the chip is mounted, the interconnecting wires are attached from the various contact pads to posts on the package (FIG. 42).
In Au wire bonding, a spool of fine Au wire (about 0.007-0.002-inch diameter) is mounted in a lead bonder apparatus, and the wire is fed through a glass or tungsten carbide capillary (FIG. 43a). A hydrogen gas flame jet is swept past the wire to form a ball on the end. In thermo-compression bonding the chip (or in some cases the capillary) is heated to about 360°C, and the capillary is brought down over the contact pad. When pressure is exerted by the capillary on the ball, a bond is formed between the Au ball and the Al pad (FIG. 43b). Then the capillary is raised and moved to a post on the package. The capillary is brought down again, and the combination of force and temperature bonds the wire to the post. After raising the capillary again, the hydrogen flame is swept past, forming a new ball (FIG. 43c); then the process is repeated for the other pads on the chip.
There are many variations in this basic method. For example, the substrate heating can be eliminated by ultrasonic bonding. In this method a tungsten carbide capillary is held by a tool connected to an ultrasonic transducer. When it is in contact with a pad or a post, the wire is vibrated under pressure to form a bond. Other variations include techniques for automatically removing the "tail," which is left on the post in FIG. 43c. When the bond to the chip is made by exerting pressure on a ball at the end of the Au wire, it is called a ball bond or a nail-head bond, because of the shape of the deformed ball after the bond is made (FIG. 44a).
Aluminum wire can be used in ultrasonic bonding; it has several advantages over Au, including the absence of possible metallurgical problems in bonds between Au and Al pads. When Al wire is used, the flame-off step is replaced by cutting or breaking the wire at appropriate points in the pro cess. In forming a bond, the wire is bent under the edge of a wedge-shaped bonding tool (FIG. 43d). The tool then applies pressure and ultrasonic vibration, forming the bond (FIG. 43e and f). The resulting flat bond, formed by the bent wire wedged between the tool and the bonding surface, is called a wedge bond. A close-up view of ball and wedge bonds is given in FIG. 44.
FIG. 43 Wire bonding techniques: (a) capillary positioned over one
of the contact pads for a ball ( nail-head) bond; (b) pressure exerted
to bond the wire to the pad; (c) post bond and flame-off; (d) wedge bonding
tool; (e) pressure and ultrasonic energy applied; (f) post bond completed
and wire broken or cut for next bond.
6.3 Flip-Chip techniques
The time consumed in bonding wires individually to each pad on the chip can be overcome by several methods of simultaneous bonding. The flip-chip approach is typical of these methods. Relatively thick metal is deposited on the contact pads before the devices are separated from the wafer. After separation, the deposited metal is used to contact a matching metallized pattern on the package substrate.
In the flip-chip method, "bumps" of solder or special metal alloys are deposited on each contact pad. These metal bumps can be distributed over the die (FIG. 45). After separation from the wafer, each chip is turned upside down, and the bumps are properly aligned with the metallization pattern on the substrate. At this point, ultrasonic bonding or solder attaches each bump to its corresponding connector on the substrate. An obvious advantage of this method is that all connections are made simultaneously. Disadvantages include the fact that the bonds are made under the chip and therefore cannot be inspected visually. Furthermore, it is necessary to heat and/or exert pressure on the chip.
6.4 Packaging
The final step in IC fabrication is packaging the device in a suitable medium that can protect it from the environment of its intended application. In most cases this means the surface of the device must be isolated from moisture and contaminants and the bonds and other elements must be protected from corrosion and mechanical shock. The problems of surface protection are greatly minimized by modern passivation techniques, but it is still necessary to provide some protection in the packaging. In every case, the choice of package type must be made within the requirements of the application and cost considerations. There are many techniques for encapsulating devices, and the various methods are constantly refined and changed. Here we shall consider just a few general methods for the purpose of illustration.
FIG. 44 Scanning electron micrographs of a ball bond (a) and a wedge
bond (b). (© 2004 Micron Technology, Inc.)
FIG. 45
Flip-chip bonding. The Power PC chip has metallized "bumps" distributed over the surface instead of contact pads around the periphery. These bumps are aligned with the interconnection pattern on the package and bonded simultaneously. (Photograph courtesy of IBM Corp.)
FIG. 46 Various types of packaging for ICs: Packages can be through-hole-mount
or surface-mount type, and be made out of plastic or ceramic. The pins can
be on one side (SIP), two sides (DIP), or four sides (quad) of the package,
or distributed over the surface of the package (PGAs or BGAs).
[Single side Dual side Full surface Single side Dual side TSOP (Thin Small-Outline Package) SOJ (Small-Outline J-Lead Package) SOP (Small-Outline Package) DIP (Dual Inline Package) PGA (Pin Grid Array) SIP (Single Inline Package) ZIP (Zig-Zag Inline Package) Through-hole mount Surface mount SVP (Surface Vertical-Mount Package) Quadruple side Full surface BGA (Ball Grid Array) QFJ (Quad Flat J-Lead Package) LCC (Leadless Chip Carrier) LCC SOJ (Leaded Chip Carrier, Small Out-Line J-Lead Package) QFP (Quad Flat Package)]
FIG. 47 Ceramic column grid array (CCGA): This advanced ceramic package
is a type of pin grid array made up of several hundred metal columns. Several
ICs with metallized solder bumps on them as in FIG. 45 can be flip-chip
bonded on the back of this package, making this a multi-chip module (MCM).
(Photograph -- IBM.)
FIG. 48 Ball grid array: In this package, the IC in the middle is wire
bonded to electrical connections on the package. The package itself has
an array of solder "balls" on the top, which can be properly aligned
and surface-mount connected simultaneously to electrical sockets on a PCB
using solder reflow. (Photograph courtesy of IBM.)
In the early days of IC technology, all devices were packaged in metal headers. In this method the device is alloyed to the surface of the header, wire bonds are made to the header posts, and a metal lid is welded over the device and wiring. Although this method has several drawbacks, it does provide complete sealing of the unit from the outside environment. This is often called a hermetically sealed device. After the chip is mounted on the header and bonds are made to the posts, the header cap can be welded shut in a controlled environment (e.g., an inert gas), which maintains the device in a prescribed atmosphere.
Integrated circuits are now mounted in packages with many output leads (FIG. 46). In one version the chip is mounted on a stamped metal lead frame and wire bonding is done between the chip and the leads. The package is formed by applying a ceramic or plastic case and trimming away the unwanted parts of the lead frame.
Broadly speaking, packages can be through-hole-mount that involve inserting the package pins through holes on the printed circuit board (PCB) before soldering, or surface-mount type where the leads do not pass through holes in the PCB. Instead, surface-mounted package leads are aligned to electrical contacts on the PCB, and are connected simultaneously by solder reflow. Most packages can be made using ceramic or plastic (which is cheaper). The ICs are hermetically sealed for protection from the environment. The pins can be on one side (single inline or zig-zag pattern of leads), two sides (dual inline package or DIP) or four sides of the package (quad package) (FIG. 46). More advanced packages have leads distributed over a large portion of the surface of the package as in through-hole-mounted pin grid arrays (PGAs) (FIG. 47) or surface-mounted ball grid arrays (BGAs) (FIG. 48). By not restricting the leads to the edges of the package, the pin count can be increased dramatically, which is very attractive for advanced ULSI in which a large number of electrical leads must be accessed.
Since a sizable fraction of the cost of an IC is due to bonding and packaging, there have been a number of innovations for automating the process. These include the use of film reels that contain the metal contact pattern onto which the chips can be bonded. The film can then be fed into packaging equipment, where the position registration capabilities of a film reel can be used for automated handling. This process, called tape-automated bonding (TAB), is particularly useful in mounting several chips on a large ceramic substrate having multilevel interconnection patterns (called a multichip module).
Summary
1. The progress of ICs can be characterized by an exponential increase in the transistor count and a corresponding decrease in feature size with time ( Moore's law). The economics are driven by device scaling and batch processing.
2. The dominant IC technology is digital CMOS, which is the basis of logic circuits (microprocessors), memories (DRAMs, SRAMs, and NVM), and application-specific ICs (ASICs).
Problems
1. In a uniform p-type Si sample, As is diffused to have a donor profile of 10^18 /cm^3 , where acceptor concentration becomes negligible in comparison of donor concentration. Find the resulting value of the sheet resistance of the diffused layer up to the junction depth of 5 µm of the device. If the mobility for electrons is µn = 500 cm^2 / V-sec, then what will be the value for the conductivity?
2. A typical sheet resistance of a base diffusion layer is 200 ohm /square.
(a) What should be the aspect ratio of a 10-kOhm resistor, using this diffusion?
(b) Draw a pattern for this resistor (see FIG. 12b) which uses little area for a width w = 5 um.
3. A 3-mm n-type epitaxial layer (Nd = 10^16 cm^-3 ) is grown on a p-type Si substrate. Areas of the n layer are to be junction isolated (see FIG. 11a) by a boron diffusion at 1200°C (D = 2.5 * 10^-12 cm^2 /s). The surface boron concentration is held constant at 10^20 cm^-3 .
(a) What time is required for this isolation diffusion?
(b) How far does an Sb-doped buried layer (D = 2 * 10^-13 cm^2 /s) diffuse into the epitaxial layer during this time, assuming the concentration at the substrate-epitaxial boundary is constant at 10^20 cm^-3 ?
4. A 500-mm-thick p-type Si wafer with a doping level of 1 * 10^15 cm^-3 has a certain region in which we do a constant source solid-solubility-limited P diffusion, resulting in a junction depth of 0.8 mm and a surface concentration of 6 * 10^19 cm^-3.
We do sheet resistance measurements on the two parts of the wafer. What is the measured sheet resistance of the p-type part? If we have a sheet resistance of 90 ohm /square in the n-type part, what is the average resistivity there?
Quiz
---Study the ITRS roadmap sections on Process, Integration, Devices and Structures (PIDS) and on Front End Processes (FEP) available at:
This has projections about next-generation CMOS devices.
• Plot some of the projected MOS device parameters from the various tables as a function of time. Do they obey Moore's law?
• Based on what you have learned in Sections 6 and 9, do the required ID(Sat) numbers for NMOSFETs for various technology nodes make sense? How about some of the other MOSFET requirements in other tables that are color-coded red?
---Discuss consequences (one good, one bad) of quantum mechanical tunneling in MOSFETs.
---What is hot electron damage, and is it more or less severe than hot hole damage? Why? How can you minimize hot carrier damage?
---Why are MOSFETs manufactured with {100} planes parallel to the Si-SiO2 interface?