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4. Charge transfer devices
One of the most interesting and broadly useful integrated devices is the charge-coupled device (CCD). The CCD is part of a broader class of structures known generally as charge transfer devices. These are dynamic devices that move charge along a predetermined path under the control of clock pulses. These devices find applications in signal processing and imaging. In this section we lay the groundwork for understanding these devices, but their present forms and variety of applications must be found in the current literature.
FIG. 15 An MOS capacitor with a positive gate pulse: (a) depletion
region and surface charge; (b) potential well at the interface, partially
filled with electrons corresponding to the surface charge shown in (a).
[3 The potential well should not be confused with the depletion region, which extends into the bulk of the semiconductor. The "depth" of the well is measured in electrostatic potential, not distance. Electrons stored in the potential well are in fact located very near the semiconductor surface.]
4.1 Dynamic Effects in MOS Capacitors
The basis of the CCD is the dynamic storage and withdrawal of charge in a series of MOS capacitors. Thus we must begin by extending the MOS discussion of Section 6 to include the basics of dynamic effects. FIG. 15 shows an MOS capacitor on a p-type substrate with a large positive gate pulse applied. A depletion region exists under the gate, and the surface potential increases considerably under the gate electrode. In effect, the surface potential forms a potential well, which can be exploited for the storage of charge.
If the positive gate bias has been applied for a sufficiently long time, electrons accumulate at the surface and the steady state inversion condition is established. The source of these carriers is the thermal generation of electrons at or near the surface. In effect, the inversion charge tells us the capacity of the well for storage charge. The time required to fill the well thermally is called the thermal relaxation time, and it depends on the quality of the semiconductor material and its interface with the insulator. For good materials the thermal relaxation time can be much longer than the charge storage times involved in CCD operation.
If instead of a steady state bias we apply a large positive pulse to the MOS gate electrode, a deep potential well is first created. Before inversion has occurred by thermal generation, the depletion width is greater than it would be at equilibrium (W 7 Wm). This transient condition is sometimes called deep depletion. If we can inject electrons into this potential well electrically or optically, they will be stored there.
3. The storage is temporary, however, because we must move the electrons out to another storage location before thermal generation becomes appreciable.
What is needed is a simple method for allowing charge to flow from one potential well to an adjacent one quickly and without losing much charge in the process. If this is accomplished, we can inject, move, and collect packets of charge dynamically to do a variety of electronic functions.
FIG. 16 The basic CCD, composed of a linear array of MOS capacitors.
At time t1, the G1 electrodes are positive, and the charge packet is stored
in the G1 potential well. At t2 both G1 and G2 are positive, and the charge
is distributed between the two wells. At t3 the potential on G1 is reduced,
and the charge flows to the second well. At t4 the transfer of charge to
the G2 well is completed.
4.2 The basic CCD
The original CCD structure proposed in 1969 by Boyle and Smith of Bell Laboratories consisted of a series of metal electrodes forming an array of MOS capacitors as shown in FIG. 16. Voltage pulses are supplied in three lines (L1, L2, L3), each connected to every third electrode in the row (G1, G2, G3). These voltages are clocked to provide potential wells, which vary with time as in FIG. 16. At time t1 a potential well exists under each G1 electrode, and we assume this well contains a packet of electrons from a previous operation. At time t2 a potential is applied also to the adjacent electrode G2, and the charge equalizes across the common G1 -G2 well. It is easy to visualize this process by thinking of the mobile charge in analogy with a fluid, which flows to equalize its level in the expanding container. This fluid model continues at t3 when V1 is reduced, thus decreasing the potential well under G1. Now the charge flows into the G2 well, and this process is completed at t4 when V1 is zero. By this process the packet of charge has been moved from under G1 to G2. As the procedure is continued, the charge is next passed to the G3 position, and continues down the line as time proceeds. In this way charge can be injected using an input diode, transported down the line, and detected at the other end.
FIG. 17 An overlapping gate CCD structure. One set of electrodes is
polycrystalline Si, and the overlapping gates are Al in this case. SiO2
separates the adjacent electrodes.
FIG. 18 A two-phase CCD with an extra potential well built in under
the right half of each electrode by donor implantation.
4.3 Improvements on the basic structure
Several problems arise in the implementation of the CCD structure of FIG. 16. For example, the separation between electrodes must be very small to allow coupling between the wells. An improvement can be made by using an over lapping gate structure such as that shown in FIG. 17. This can be done, for example, with poly-Si electrodes separated by SiO2 or with alternating poly-Si and metal electrodes.
One of the problems inherent to the charge transfer process is that some charge is inevitably lost during the many transfers along the CCD. If the charges are stored at the Si-SiO2 interface, surface states trap a certain amount of charge. Thus if the "0" logic condition is an empty well, the leading edge of a train of pulses is degraded by the loss of charge required in filling the traps which were empty in the "0" condition. One way of improving this situation is to provide enough bias in the "0" state to accommodate the interface and bulk traps. This procedure is colorfully referred to as using a fat zero. Even with the use of fat zeros, the signal is degraded after a number of transfers, by inherent inefficiencies in the transfer process.
Transfer efficiency can be improved by moving the charge transfer layer below the semiconductor-insulator interface. This can be accomplished by using ion implantation or epitaxial growth to create a layer of opposite type than the substrate. This shifts the maximum potential under each electrode into the semiconductor bulk, thus avoiding the semiconductor-insulator interface. This type of device is referred to as a buried channel CCD.
The three-phase CCD shown in FIG. 16 is only one example of a variety of CCD structures. FIG. 18 illustrates one method for achieving a two-phase system, in which voltages are sequentially applied to alternating gate electrodes from two lines. A two-level poly-Si gate structure is used, in which the gate electrodes overlap, and a donor implant near the Si surface creates a built-in well under half of each electrode. When both gates are turned off (b), potential wells exist only under the implanted regions, and charge can be stored in any of these wells. With electrode G2 pulsed positively, the charge packet shown in (b) is transferred to the deepest well under G2, which is its implanted region as (c) indicates. Then with both gates off, the wells appear as in (b) again, except that the charge is now under the G2 electrode. The next step in the transfer process is obviously to pulse G1 positively, so that the charge moves to the implanted region under the G1 electrode to the right.
Other improvements to the basic structure are important in various applications. These include channel stops or other methods for achieving lateral confinement for the stored charge. Regeneration points must be included in the array to refresh the signal after it has been degraded.
FIG. 19 A charge-coupled device image sensor shown as large white rectangular
areas, with peripheral signal processing circuitry. (Texas Instruments.)
4.4 Applications of CCDs
CCDs are used in a number of ways, including signal processing functions such as delay, filtering, and multiplexing several signals. Another interesting application of CCDs is in imaging for astronomy or in solid state cameras, in which an array of photosensors is used to form charge packets proportional to light intensity, and these packets are shifted to a detector point for readout. There are numerous ways of accomplishing this in CCDs, including the linear array line scanner, in which the second dimension is obtained by moving the scanner relative to the image. Alternatively, an area image sensor can be made which scans the image electronically in both dimensions. The latter device can be used as an alternative to the electron beam-addressed television imaging tube (FIG. 19).
FIG. 20 Size reduction of a 256-Mb DRAM die as the minimum feature
size is reduced from 0.13 um for the first-generation design (die on the
left) to 0.11 um for the die on the right. (© 2004 Micron Technology, Inc.)
FIG. 21 Three ways of obtaining 128 million bits of DRAM: (a) one 128-Mb
chip; (b) two 64-Mb chips; (c) eight 16-Mb chips. The 128-Mb die measures
almost 1 by 1 inch. (2004 Micron Technology, Inc.).