Switching-Mode Power Supplies--Push-Pull and Forward Converter Topologies [part 3]

<< cont. from part 2

4. Double-Ended Forward Converter Topology

4.1 Basic Operation

FIG. 13 Double-ended forward converter. Transistors Q1 and Q2are turned on and off simultaneously. Diodes D1 and D2 keep the maximum off-voltage stress on Q1, Q2 at a maximum of Vdc as contrasted with 2Vdc plus a leakage spike for the single-ended forward converter of FIG. 10.

Double-ended forward converter topology is shown in FIG. 13.

Although it has two transistors rather than one compared with the single-ended forward converter of FIG. 10, it has a very significant advantage. In the "off" state, both transistors are subjected to only the DC input voltage rather than twice that, as in the single-ended converter. Further, at turn "off," there is no leakage inductance spike.

It was pointed out in Section 2.3.7 that the off-voltage stress in the single-ended forward converter operating from a nominal 120-V AC line can be as high as 550 V when there is a 15% transient above a 10% steady-state high line and a 30% leakage spike.

Although a number of bipolar transistors have Vcev ratings up to 650 and even 850 V that can take that stress, it is far more reliable to use a double-ended forward converter with half the off-voltage stress.

Reliability is of overriding importance in a power supply design, and in any weighing of reliability versus initial cost, the best and-in the long run-least expensive choice is reliability.

Further, for power supplies to be used in the European market where the AC voltage is 220V(rectified DC voltage is nominally about 308 V), the single-ended forward converter is not usable at all because of the excessive voltage stress on the off transistor (see Eqn. 29). The double-ended forward converter, the half bridge, and the full bridge (to be discussed in Section 3) are the only choices for equipment to be used in the European market.

The double-ended forward converter works as follows. In FIG. 13, Q1 and Q2 are in series with the transformer primary. These transistors are turned on and off simultaneously. When they are "on," all primary and secondary dot ends are positive, and power is delivered to the loads. When they turn "off," current stored in the T1 magnetizing inductance reverses the voltage polarity of all windings. The negative-going dot end of Np is caught at ground by diode D1, and the positive-going no-dot end of Np is caught at Vdc by diode D2.

Thus the emitter of Q1 can never be more than Vdc below its collector, and the collector of Q2 can never be more than Vdc above its emitter. Leakage inductance spikes are clamped so that the maximum voltage stress on either transistor can never be more than the maxi mum DC input voltage.

The further significant advantage is that there is no leakage inductance energy to be dissipated. Any energy stored in the leakage inductance is not lost by dissipation in some resistive element or in the power transistors. Instead, energy stored in the leakage inductance during the "on" time is fed back into Vdc via D1 and D2 when the transistors turn "off." The leakage inductance current flows out of the no-dot end of Np, through D2, into the positive end of Vdc, out of its negative end, and up through D1 back into the dot end of Np.

Examination of FIG. 13 reveals that the core is always reset in a time equal to the "on" time. The reverse polarity voltage across Np when the transistors are "off" is equal to the forward polarity voltage across it when the transistors are "on." Thus the core will always be fully reset with a 20% safety margin before the start of a succeeding half cycle if the maximum "on" time is no greater than 80% of a half period. This is accomplished by choosing secondary turns so that the peak secondary voltage at minimum Vdc times the maximum duty cycle of 0.4 equals the desired output voltage (see Eqn. 25).

4.1.1 Practical Output Power Limits

It should be noted that this topology still yields only one power pulse per period, just like the single-ended forward converter. Thus the power available from a specific core is pretty much the same for either the single- or double-ended configuration. As noted in Section 2.3.10.6, the reset winding in the single-ended circuit carries only magnetizing current during the power transistor "off" time. Since that current is small, the reset winding can be wound with very small wire. Thus, the absence of a reset winding in the double-ended circuit does not permit significantly larger power winding wire size and output power from a given core.

Because the maximum off transistor voltage stress cannot be greater than the maximum DC input voltage, however, the 200-W practical power limit for the single-ended forward converter discussed in Section 2.3.7 does not hold for the double-ended forward converter. With the reduced voltage stress, output powers of 400 to 500Ware obtain able, and transistors with the required voltage and current capability and adequate gain are available at low price.

Consider a double-ended forward converter operating from a nominal 120-V AC line with ± 10% tolerance and ± 15% allowance for transients on top of that. The maximum rectified DC voltage is 1.41 × 120 × 1.1 × 1.15 = 214 V, and the minimum rectified DC voltage is 1.41 × 120÷1.1÷1.15 = 134V, and equivalent flat-topped primary current from Eqn. 28 is Ipft = 3.13Po /Vdc, and for Po = 400W, Ipft = 9.6A.

This requirement can be satisfied quite easily, because both bipolar and MOSFET transistors with adequately high gain are available at low cost.

A double-ended forward converter with a voltage doubler from the 120-V AC line would be a better alternative. This would double the voltage stress to 428 V but would halve the peak current to 4.8A.With 4.8Aof primary current, RFI problems would be less severe. A bipolar transistor with a 400-V Vceo rating could tolerate 428 V easily, with -1- to -5-V reverse bias at the instant of turn "off" (Vcev rating).

4.2 Design Relations and Transformer Design

4.2.1 Core Selection-Primary Turns and Wire Size

The transformer design for the double-ended forward converter proceeds exactly as for the single-ended converter. A core is selected from the aforementioned selection charts (to be presented in Section 7 on magnetics) for the required output power and operating frequency.

The number of primary turns is chosen from Faraday's law as in Eqn. 40. There the minimum primary voltage is (Vdc - 2) as there are two transistors rather than one in series with the primary-but the transistor drops are insignificant since Vdc is usually 134 V (120 V AC). Maximum "on" time should be set at 0.8T/2 and dB at 1600 G up to 50 kHz, or higher if not limited by core losses.

As mentioned for frequencies from100 to 300 kHz, peak flux density may have to be set from about 1400 to 800 G, as core losses increase with frequency. But the exact peak flux density chosen depends on whether the newer, lower-loss materials are available. It also depends to some extent on transformer size-smaller cores can generally operate at higher flux density, because they have a larger ratio of radiating surface area to volume and hence can get rid of the heat they generate (which is proportional to volume) more easily.

Since there is only one current or power pulse per period, as in the single-ended forward converter, the primary current for a given output power and minimum DC input voltage is given by Eqn. 28, and the primary wire size is chosen from Eqn. 42.

4.2.2 Secondary Turns and Wire Size

Secondary turns are chosen exactly as in Sections 3.2 and 3.3 from Eqs. 25 to 27. Wire sizes are calculated as in Section 3.10.5 from Eqn. 44.

4.2.3 Output Filter Design

The output inductor and capacitor magnitudes are calculated exactly as in Section 3.11 from Eqs. 46 to 48.

5. Interleaved Forward Converter Topology

5.1 Basic Operation-Merits, Drawbacks, and Output Power Limits

This topology is simply two identical single-ended forward converters operating on alternate half cycles with their secondary currents adding through rectifying "on" diodes. The topology is shown in Figure 2.14.

The advantage, of course, is that now there are two power pulses per period, as seen in FIG. 14, reducing the ripple current; also each converter supplies only half the total output power.

Equivalent flat-topped peak transistor current is derived from Eqn. 28 as Ipft = 3.13 Pot/2Vdc where Pot is the total output power.

This transistor current is half that of a single forward converter at the same total output power. Thus the expense of two transistors is offset by the lower peak current rating and lower cost than that of the higher current rating device.

Looking at it another way, two transistors of the same current rating used at the same peak current as one single-ended converter at a given output power in an interleaved converter would yield twice the output power of the single converter.

Also, since the intensity of EMI generated is proportional to the peak current, not to the number of current pulses, an interleaved converter of the same total output power as a single forward converter will generate less EMI.

FIG. 14 Interleaved forward converter. Interleaving the "on" times of Q1 and Q2 on alternate half cycles, and summing their secondary outputs, gives two power pulses per period but avoids the flux-imbalance problem of the push-pull topology.

If this topology is compared to a push-pull, it might be thought that the push-pull is preferable. Although both are two-transistor circuits, the two transformers in the interleaved forward converter are probably more expensive and occupy more space than a single large one in a push-pull circuit. But there is the ever-present uncertainty that the flux imbalance problem in the push-pull could appear under odd transient line and load conditions. The certainty that there is no flux imbalance in the interleaved forward converter is probably the best argument for its use.

There is one special, although not frequent, case where the inter leaved forward converter is a much more desirable choice than a single forward converter of the same output power. This occurs when a DC output voltage is high-over about 200 V. In a single forward converter the peak reverse voltage experienced by the output free wheeling diodes (D5A or D5B) is twice that for an interleaved forward converter as the duty cycle in the latter is twice that in the former.

This is no problem when output voltages are low, as can be seen in Eqn. 25. Transformer secondary turns are always selected (for the single forward converter) so that at minimum DC input, when the secondary voltage is at its minimum, the duty cycle Ton/T need not be more than 0.4 to yield the desired output voltage. Then for a DC output of 200 V, the peak reverse voltage experienced by the free wheeling diode is 500 V. At the instant of power transistor turn "on," the free-wheeling diode has been carrying a large forward current and will suddenly be subjected to reverse voltage. If the diode has slow reverse recovery time, it will draw a large reverse current for a short time at 500-V reverse voltage and run dangerously hot.

Diodes with larger reverse voltage ratings generally have slower recovery times and can be a serious problem. The interleaved forward converter runs at twice the duty cycle and, for a 200 V-DC output, subjects the free-wheeling diode to only 250 V. This permits a lower voltage, faster-recovery diode with considerably lower dissipation.

5.2 Transformer Design Relations

5.2.1 Core Selection

The core for the two transformers will be selected from the aforementioned charts, to be presented in Section 7, but it will be chosen for half the total power output that each transformer must supply.

5.2.2 Primary Turns and Wire Size

The number of primary turns in the interleaved forward converter is still given by Eqn. 40, as each converter's "on" time will still be 0.8T/2 at minimum DC input. The core iron area Ae will be read from the catalogs for the selected core. Primary wire size will be chosen from Eqn. 42 at half the total output power.

5.2.3 Secondary Turns and Wire Size

The number of secondary turns will be chosen from Eqs. 26 and 27, but therein the duty cycle will be 0.8 as there are two voltage pulses, each of duration 0.8T/2 at Vdc. Wire size will still be chosen from Eq. 44, where Idc is the actual DC output current that each secondary carries at a maximum duty cycle of 0.4.

5.3 Output Filter Design

5.3.1 Output Inductor Design

The output inductor sees two current pulses per period, exactly like the output inductor in the push-pull topology. These pulses have the same width, amplitude, and duty cycle as the push-pull inductor at the same DC output current. Hence the magnitude of the inductance is calculated from Eqn. 20 as for the push-pull inductor.

5.3.2 Output Capacitor Design

Similarly, the output capacitor "doesn't know" whether it is filtering a full-wave secondary waveform from a push-pull topology or from an interleaved forward converter. Thus for the same inductor cur rent ramp amplitude and permissible output ripple as the push-pull circuit, the capacitor is selected from Eqn. 22.

Also see: