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7. COMPONENT QUALIFICATION
Qualification tests are conducted to make a prediction about the fielded reliability of a product and its chance of success in fulfilling its intended application. Component qualification was established as an experimental means to answer the following two questions.
1. Will the component function in the application as designed?
2. Will the component function as intended for the life of the product? Since specific ICs are typically the most critical components in a given product design (providing its market differentiation), the discussion on qualification will be focused specifically on ICs. However, the underlying points made and concepts presented are applicable to the qualification of all components.
We look first at what was done in the past in qualifying components to give us a perspective on where we've come from. Next I examine current qualification methodologies and follow this with a discussion of what will likely be required in the future. Finally, I provide a list of items to consider in developing a component qualification strategy.
(coming soon) Table 12 Typical IC Qualification Tests
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(coming soon) TABLE 13 Traditional IC Qualification Test Practices
Stress test response-driven qualification uses a one-size-fits-all test mindset.
The wrong tests are performed.
The stresses aren't compatible with nor do they provide an assessment of current technology.
The tests can be interpreted incorrectly.
The tests are statistically insignificant and do not reflect process variations over the IC's life. The small sample size drawn from one or two production runs yielded results that were statistically meaningless and incapable of identifying any problems associated with wafer fabrication or assembly process variations. If the qualification tests were conducted on preproduction or ''learning lots,'' no valid interpretation of the data gathered could be made.
The tests are too expensive to perform.
The tests take too long to perform, negatively impacting time to market.
The standards require using a large sample size resulting in too many ICs being destroyed.
The tests don't include application requirements.
The test structure doesn't take into account the impact of change (design, wafer fab, assembly, and test processes).
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7.1 Qualification Testing in the Past
Integrated circuit qualification tests prior to the 1990s were one-time events con ducted by the user (OEM) or by the supplier for a specific customer under the customer's direction. They used a one-size-fits-all stress-driven methodology based on MIL-STD-883, rather than on specific application requirements. Table 12 lists the typically conducted qualification tests. Notice that 1000-hr operating life and storage tests are included to make an assessment of the long-term reliability of the IC.
Qualification testing was typically conducted just prior to release to production; it was long (the typical time to complete device qualification testing was 4-6 months or longer), costly (direct costs varied from $10,000 to $50,000 or more per device/package type and costs associated with system testing and product introduction delays added several orders of magnitude to this number), and destroyed many expensive ICs in the process (an ASIC, FPGA, or microprocessor can cost between $500 and $3,000 each). For an ASIC, one could use (destroy) the entire production run (1-3 wafers) for qualification testing-truly unrealistic.
Table 13 lists the issues with the traditionally used stress test-driven qualification test practices.
When the leadership in the military/aerospace community decided that the best way for inserting the latest technological component developments into their equipment was to use commercial off-the-shelf (COTS) components, the commercial and semiconductor industries looked to EIA/JESD 47 and JESD 34 to replaceMIL-STD-883 for IC qualification testing. The following is a brief discussion of these standards.
Stress Test-Driven Qualification
EIA/JESD Standard 47 (stress test-driven qualification of integrated circuits) contains a set of the most frequently encountered and industry-accepted reliability stress tests. These tests (like those of MIL-STD-883), which have been found capable of stimulating and precipitating IC failures in an accelerated manner, are used by the IC supplier for qualifying new and changed technologies, processes, product families, as well as individual products.
The standard is predicated on the supplier performing the appropriate tests as determined by the IC's major characteristics and manufacturing processes. It states that each qualification project should be examined for
1. Any potential new and unique failure mechanisms
2. Any situations where these tests/conditions may induce failures
In either case the set of reliability requirements and tests should be appropriately modified to properly address the new situations in accordance with JESD 34.
Failure Mechanism-Driven Reliability Qualification
JESD 34 (failure mechanism-driven qualification of silicon devices) provides an alternative to traditional stress-driven qualification for mature products/manufacturing processes. (As a side note, both JESD 34 and EIA/JESD 47 were developed by an industry consortium consisting mainly of IC suppliers and thus have their buy-in.) This standard is predicated on accepting the qualification process performed by the supplier using qualification vehicles rather than actual product.
Thus, JESD 34 does not address qualification of product, quality, or functionality.
The standard is based on the fact that as failure rates (and thus the number of detectable defects) become smaller, the practice of demonstrating a desired reliability through the use of traditional stress-driven qualification tests of final product becomes impractical. The burden for this method of qualification falls on the shoulders of the IC supplier (as it should) through an understanding of the wafer fab and assembly processes, potential failure mechanisms of familiar products/ processes; and the implementation of an effective in-line monitoring process of critical parameters. The standard provides a typical baseline set of reliability qualification tests.
From an OEM perspective there are several problems with this approach, including
The supplier is not in a position to determine the impact that various failure mechanisms have on system performance.
The method does not take into account functional application testing at the system level, which is really the last and perhaps most important step in component qualification.
Also, OEMs are active participants of failure mechanism-driven qualification by committing to collect, analyze, and share field failure data with the sup plier. Then, from this data, the supplier identifies those failure mechanisms that may be actuated through a given product/process change and develops and implements reliability tests that are adequate to assess the impact of those failure mechanisms on system reliability.
7.2 Current Qualification Methodology
The component world has changed, as has the method of achieving component qualification. Stress test-driven qualification conducted by the supplier is an important and necessary part of component qualification, but it is not sufficient for today's (and future) technologies and components. Much more is needed to qualify an IC for use than is covered by either stress test-driven qualification or failure mechanism-driven qualification. The qualification test process must be compatible with the realities of both the technology and business requirements.
It must leverage the available tools and data sources other than traditional IC life tests. The methodology focuses on reliability issues early in the design phase, ensuring that product reliability goals and customer expectations are met; it optimizes cost and cycle time; and it stimulates out-of-box thinking.
Today, IC qualification
Is a dynamic multifaceted process Is application specific and determined, in the final analysis, by various sys tem tests Is based on an understanding of the specific potential failure mechanisms for the device and technology proposed for use in a specific application Requires a clear understanding of the roles and responsibilities of the IC supplier and IC user (OEM) in qualifying components for use The current qualification methodology recognizes that there are two distinct partners responsible for qualification testing of a given component. It is a cooperative effort between IC suppliers and OEMs, with each party focusing their time and energy on the attributes of quality and reliability that are under their respective spheres of control. The industry has moved from the OEMs essentially conducting all of the environmental and mechanical qualification tests to the IC suppliers performing them to ensure the reliability of their components.
The IC suppliers have the sole responsibility for qualifying and ensuring the reliability, using the appropriate simulations and tests, for the components they produce. Identification of reliability risks just prior to component introduction is too late; qualification must be concurrent with design. By implementing a design-for-reliability approach, IC suppliers minimize reliance on conventional life tests. Instead, they focus on reliability when it counts-during the IC circuit, package design, and process development stages using various validation vehicles and specially designed test structures to gather data in a short period of time. This IC qualification approach has been validated through the successful field performance of millions of parts in thousands of different fielded computer installations.
The component suppliers are also asked to define and verify the performance envelope that characterizes a technology or product family. They do this
7.2 Current Qualification Methodology
The component world has changed, as has the method of achieving component qualification. Stress test-driven qualification conducted by the supplier is an important and necessary part of component qualification, but it is not sufficient for today's (and future) technologies and components. Much more is needed to qualify an IC for use than is covered by either stress test-driven qualification or failure mechanism-driven qualification. The qualification test process must be compatible with the realities of both the technology and business requirements.
It must leverage the available tools and data sources other than traditional IC life tests. The methodology focuses on reliability issues early in the design phase, ensuring that product reliability goals and customer expectations are met; it optimizes cost and cycle time; and it stimulates out-of-box thinking.
Today, IC qualification Is a dynamic multifaceted process Is application specific and determined, in the final analysis, by various sys tem tests Is based on an understanding of the specific potential failure mechanisms for the device and technology proposed for use in a specific application Requires a clear understanding of the roles and responsibilities of the IC supplier and IC user (OEM) in qualifying components for use The current qualification methodology recognizes that there are two distinct partners responsible for qualification testing of a given component. It is a cooperative effort between IC suppliers and OEMs, with each party focusing their time and energy on the attributes of quality and reliability that are under their respective spheres of control. The industry has moved from the OEMs essentially conducting all of the environmental and mechanical qualification tests to the IC suppliers performing them to ensure the reliability of their components.
The IC suppliers have the sole responsibility for qualifying and ensuring the reliability, using the appropriate simulations and tests, for the components they produce. Identification of reliability risks just prior to component introduction is too late; qualification must be concurrent with design. By implementing a design-for-reliability approach, IC suppliers minimize reliance on conventional life tests. Instead, they focus on reliability when it counts-during the IC circuit, package design, and process development stages using various validation vehicles and specially designed test structures to gather data in a short period of time. This IC qualification approach has been validated through the successful field performance of millions of parts in thousands of different fielded computer installations.
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(coming soon) TABLE 14 Example of an IC Supplier Qualification Process: Elements and Responsibilities
Process technology qualification through advanced process validation vehicles, test structures (WLR), and packaged devices FEOL wearout: Vt stability, gate dielectric integrity, HCI, TDDB BEOL wearout: EM (in both Al and Cu metal lines and vias), stress voiding/ migration, ILD integrity Manages potential wearout mechanisms through robust design rules and process control Verifies that design simulations using sophisticated and accurate CAD, SPICE, and reliability models correlate with physical failure mechanisms and reliability design rules and validates that they match the wafer fab process.
Controls process reliability interactions by management of critical process steps.
Reliability monitors, WLR test structures, and qualification test data are used to verify reliability projections.
Conducts package reliability tests Computer simulations and tests are conducted for new package types and interconnect technologies (e.g., flip chip), without the die in the package, for assembly compatibility/manufacturability, materials compatibility, thermal characteristics, and electrical performance (parasitic effects) Wire bonding Die attach Solderability Moisture performance
Prerequisites for conducting complete IC qualification testing Topological and electrical design rules established and verified. There is a good correlation between design rules and wafer fab process models.
Verifies that die package modeling (simulation) combination for electrical and thermal effects matches the results obtained with experimenting testing.
Comprehensive characterization testing is complete including four-corner (process) and margin tests at both NPI and prior to each time a PCN is generated, as appropriate.
Electrical test program complete and released.
Data sheet developed and released.
Manufacturing processes are stable and under SPC.
In-line process monitors are used for real-time assessment and corrective action of critical process or product parameters with established Cpk metrics and to identify escapes from standard manufacturing, test, and screening procedures (maverick lot).
Conducts complete IC qualification tests Conducts electrical, mechanical and environmental stress tests that are appropriate for the die, package, and interconnection technologies used and potential failure mechanisms encountered and to assess time-dependent reliability drift and wear out.
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The component suppliers are also asked to define and verify the performance envelope that characterizes a technology or product family. They do this by conducting a battery of accelerated testing (such as 1000-hr life tests) for the electrical function and technology being used in the design: wafer fab process, package and complete IC. From these tests they draw inferences (projections) about the field survivability (reliability) of the component. Additionally, a commitment in supplying high-quality and high-reliability ICs requires a robust quality system and a rigorous self-audit process to ensure that all design, manufacturing, electrical test, continuous improvement, and customer requirement issues are being addressed.
Table 14 details the tasks that the IC supplier must perform to qualify the products it produces and thus supply reliable integrated circuits. Notice the focus (as it must be) is on qualifying new wafer fabrication technologies. Equally important is the effort required to conduct the appropriate analyses and qualification and reliability tests for new package types and methods of interconnection, since they interconnect the die to the PWA, determine IC performance, and have an impact on product reliability.
The user (OEM) requires a stable of known good suppliers with known good design and manufacturing processes. This begins with selecting the right technology, part, package, and supplier for a given application early in the design phase, within an organizational structure that is focused on supplier management.
The use of standard off-the-shelf components (such as those used in personal computers or mobile applications) should be encouraged since they drive the marketplace by their volume, process improvements, and process stability. But it must also be realized that product leverage often comes from using sole-sourced "bleeding-edge" components. The use of sole-sourced components presents unique product qualification issues due to the dependence of the product design on a single part and the need for continued availability of that part throughout the product manufacturing cycle. If the part becomes unavailable for any reason and the PWA must be redesigned to accommodate another part or requires a mezzanine card (which still entails somewhat of a PWA relay out), portions or all of the qualification process must be repeated. The price paid for this is added cost and delay of the product's market introduction. The critical element of successful component qualification, for both the present and the future, is OEM conducted application-based (also called functional application) testing.
Different market segments/system applications have different component qualification requirements. Table 15 lists examples of some of the different requirements of various market segments. The OEM must first determine what components are critical to a design for a given end market (application) and then tailor the tests for these critical components and their associated PWAs to be compatible with the specific application needs. The OEM makes an assessment of the survivability of the product/equipment in the field with all components, modules, and subassemblies integrated into the design by conducting a battery of end use-specific tests.
Application testing has traditionally been the OEM's responsibility, but in the PC world suppliers are often given machines (computers) to run the application testing per OEM-provided documentation. This allows the OEMs to potentially qualify a number of suppliers simultaneously, ensuring a plentiful supply of low-priced parts.
The high-end PC server OEMs look at all components, but instead of qualifying each component, they qualify a family of devices (like ASICs and other commodities) with the same manufacturing process. The automotive industry essentially tells the supplier what tests to conduct and then they run the same tests on varying sample sizes. Automotive OEMs don't have the same level of trust of their suppliers, and they are always looking for lowest price rather than lowest overall cost (total cost of ownership).
(coming soon) TABLE 15 Examples of End Market Qualification Test Needs
Personal computer OEMs perform detailed specification reviews and con duct application tests. In some specific instances they may have the supplier do some special analyses and tests. Consumer product providers and low-end PC companies just rely on normal supplier qualification procedures and application tests that just look at the ability of different suppliers' parts to "play well" together.
Table 16 is a detailed list of the steps that the OEM of a complex electronic system takes in qualifying critical components for use in that system, both currently and looking to the future.
7.3 Forward-Thinking Qualification
One thing is for certain, technology improvements and market conditions will require suppliers and OEMs alike to continually review, evaluate, refine, and update the techniques and processes used to qualify both ICs (components) and products. New methods will need to be developed to keep pace with the following expected component technology improvements and market conditions.
1. Shorter product design and life cycles. The PC and consumer (mobile appliance) markets are spearheading a drive to shorter product design cycles. The pressure to keep up with technology changes is causing decreased design cycles for all electronic products (PCs, servers, mainframe computers, telecommunication equipment, and consumer products). Time to market is the key to market share and profitability; therefore, short product design cycles are here to stay.
Newer designs face greater time-to-market pressures than previous designs. For example, new PCs are being released to production every 4 months versus every 6-9 months previously. In order to support these short design cycles and in creased design requirements, component qualification processes must be relevant and effective for this new design environment. Figure 11 shows the dramatically shortened product design and qualification timeframes.
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(coming soon) TABLE 16 Example of Complex Equipment OEM's Qualification Model for Critical Components
1. Supplier business qualification. Is the company stable, financially viable, a good business and technology partner? (Responsibility: Purchasing)
2. Supplier technology qualification. Is this a viable/producible technology? (Responsibility: Technology Development and Component Engineering)
3. Supplier line qualification [wafer fabrication and assembly (ICs) and manufacturing (components)]. Can the parts be built reliably, consistently, and to OEM requirements? (Responsibility: Component Engineering and Supplier Quality Engineering)
4. Review supplier in-line process monitors, die and assembly qualification test data, and wafer level reliability test data (for ICs). (Responsibility: Component Engineering and Supplier Quality Engineering).
5. In-product application qualification tests and evaluations:
a. Manufacturability test (on PWA for new package type-wash, solderability, etc.). Is the part compatible with our manufacturing process? (Responsibility: Manufacturing Engineering)
b. SPICE and CAD models and supplier provided tools (for ICs). Are the models and tools available and ready for use? Can the component operate to our requirements? (Responsibility: Product Technology Modeling and Simulation)
c. Test vector qualification (for ICs). Is there a high (_95%) level of test/fault coverage? Are a combination of AC, DC, IDDQ , functional (stuck at), delay, and at-speed tests utilized to ensure the performance of the component? Is there a high correlation between electrical test yield, test coverage, and average outgoing quality level? Does wafer test yield correlate with final electrical test yield? (Responsibility: Technology Development)
d. Smorgasbord (Smorgy) testing (mix and match all suppliers of multi-sourced components on the PWA. Can the different suppliers for a given part work in the application together? (Responsibility: Product Design and Product Quality Engineering)
e. Matrix lot testing. Can the component be manufactured to consistently meet requirements even in a worst case/worst use environment? What are the operating margins/boundaries and safe design space (parts are manufactured at the process corners and tested on the PWA)? Will the components operate in the PWA to requirements (timing and signal integrity)? (Responsibility: Product Design for conducting tests/evaluations; Component Engineering for communicating requirements to suppliers and tracking completion of manufacturing parts at corners)
f. Special studies.
What are the non-specified parameters that are critical to the application? The OEM performs reliability assessments, package studies (e.g., PWA solderability, lead-free evaluation), thermal studies, signal integrity testing, and electrical tests of critical IC parameters, often unspecified by the supplier, for proper system functioning. The latter includes timing analysis, cross-talk, ground bounce, simultaneous switching outputs, undershoot, power-on ramp/surge, and the like. (Responsibility: Component Engineering and Design Engineering)
g. HALT testing at PWA or module (subassembly) level. Highly accelerated stress tests in which power cycling, temperature, temperature cycling, and random vibration testing are used simultaneously to take a product beyond its design requirements to determine its robustness (more about this in Section 7).
(Responsibility: Product Design and Product Quality Engineering)
h. System test. Do the components work in the system as designed and intended? (Responsibility: Product Design)
6. PWA manufacturing ICT and manufacturing ATE functional qualification. Has the component been degraded due to test overdrive? (Responsibility: Manufacturing Engineering)
7. Supplier process change monitoring (as required).
a. Destructive physical analysis. Has anything in the physical assembly of the component changed? (Responsibility: Component Engineering and Supplier Quality Engineering)
b. Periodic manufacturing line auditing. Using SPC data it answers the question has anything changed (drifted) in wafer fabrication. (Responsibility: Component Engineering and Supplier Quality Engineering)
c. Requalification of supplier processes based on process change notification being received. (Responsibility: Component Engineering and Supplier Quality Engineering)
8. Product requalification due to process change notification impacting product performance. (Responsibility: Product Design Engineering)
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1. The changing process and product qualification timeframe.
Traditional back-end stress-based qualification test methods will not meet the short cycle times for today's market. Integrated circuit suppliers need to develop faster and more effective technology and process-qualification methods (test vehicles and structures) that give an indication of reliability before the IC design is complete.
2. Shorter component life cycles. Component production life cycles have significantly been reduced over the last 5-10 years. A typical component has a 2- to 4-year production life cycle (time to major change or obsolescence).
The shortened component life cycle is due to the effect of large PC, telecommunication equipment, and consumer product manufacturers pressuring component suppliers for cost reductions until a part becomes unprofitable to make. Often, a reduction in demand causes component manufacturers to make obsolete devices that are suddenly unprofitable to produce. A second factor reducing component life cycles is large equipment manufacturers discontinuing products due to technological obsolescence and market pressure to provide the latest technologies in their products.
3. Complications of high-speed designs. The design of high-speed circuits adds many complications that affect component qualification, such as high frequency operation, timing variances, and signal quality. Maximum IC operating frequency specifications are being driven by newer and faster designs. In order to develop components that are faster, suppliers are reducing rise and fall times, which affect functionality in high-speed applications. The resultant decreasing setup and hold times cause minimal propagation delays to become critical as well. The effect of these shorter rise and fall times must be considered in IC qualification. Designing for high-speed logic applications is very difficult and requires the use of transmission line design techniques to ensure good signal quality. Both IC and product designers are responsible for signal quality. The increased power dissipation and resultant thermal issues generated by these high operating speeds must be addressed as well (See Sections 3 and 5 for more details).
4. Highly integrated component designs. The highly integrated component designs such as system-on-a-chip, high-density ASICs, and field-programmable gate arrays add special challenges. How do you qualify the RAM embedded within a larger device? How do you characterize the performance of a component that is configured prior to use while embedded in the application? Highly integrated component designs add the failure mechanism of different component types onto one chip. Component qualification must consider the failure mechanisms of all of the parts that make up a highly integrated device (i.e., microprocessors, RAM, PLLs, logic, mixed signal, etc.).
Also added to these are:
More complex electrical test programs and shorter allowed test program development time.
More complex package qualification.
The package is an integral part of the complete IC solution from electrical performance, thermal management, and mechanical protection perspectives.
Stacked packages present new and unique issues.
Faster time to market and shorter component qualification times.
Less components to qualify.
More knowledge of component required.
More application (product) knowledge required.
Shorter product change notice review. IC suppliers make a myriad planned and unplanned die shrinks to reduce wafer costs and improve IC performance. This requires that they conduct the appropriate tests and analyses prior to issuing a product change notice (PCN). They want to have a shorter PCN review cycle so they can quickly get into production with the proposed changes. But the OEM needs time to evaluate these changes and their impact on the circuit design, often requiring expensive and time-consuming system requalification testing.
Greater quality and reliability expectations.
High-speed highly integrated and complex product designs.
7.4 Application-Based Qualification: The Future
The environmental and mechanical "shake-and-bake" testing philosophy of component qualification as espoused by MIL-STD-883 has become entrenched into our component qualification philosophy. For some product environments stress-based qualification testing is still a critical aspect of component qualification that cannot be discounted. Stress test-based component qualification testing addresses the physical attributes that cause early-life failures, but does not address all aspects of electrical or functional fitness for the application that uses the component.
For product designs of the new millennium component qualification focuses on two critically important areas from an OEM perspective: a consideration of the application requirements and qualifying the technology that creates the components (rather than qualify the resulting output of the technology; i.e., the specific component). Application-based qualification allows a family of components to be qualified and maintained for its lifetime with review of technology data and the results of changes in a product family. This approach results in reduced component qualification cycle times and provides the means to perform an engineering analysis of supplier-provided data to evaluate a component product change versus the "try one and see if it fails" approach.
The fundamental difference between application-based qualification and traditional component qualification is understanding what a technology can and cannot do; how it behaves with various loading conditions versus testing a component to a data sheet; and the specific application requirements. However, not all is new. Component qualification is an evolutionary process that meets the current time period technology realities and market needs. Many aspects of application-based qualification are already in place and operating out of necessity. As mentioned in Section 3, the OEM's technology needs must be matched with the supplier's technology availability (see Fig. 2 of Section 3). Passing qualification is an assessment that there is a low level of risk that a technology will have issues in user applications.
Application-Based Qualification Details
1. Identifying device technology and system requirements. The engineer responsible for qualifying a device needs to understand both the device technology requirements and the application requirements. This knowledge is gained in part by working closely with the responsible product design engineer. Thus, the qualifying engineer is an expert consultant for new application uses of previously qualified devices and technologies.
2. Quality assessment. Supplier qualification is a prerequisite to application-based qualification. After a supplier is qualified, a quality assessment of the technology being qualified should begin. Process quality attributes that affect quality and reliability should be evaluated. These include Quality. Conformance to data sheet specifications (see following paragraph on self-qualification) and process control (accuracy, stability, repeatability, and reproducibility) Reliability. Wearout (i.e., high-temperature operating life, gate oxide dielectric integrity, hot carrier degradation, electromigration, etc.) Susceptibility to stress. Electrostatic discharge, latch-up, electromigration, delamination, etc.
Soft error rate (SER). Transient errors caused by alpha particles and cos mic rays (devices with memory cells)
3. Self-qualification process. The majority of a technology qualification's requirements can be satisfied by the supplier's submission of information on a device technology via a self-qualification package. The self-qualification package should address the technology attributes that define the technology limits and process capability. Device characterization data showing minimum, maxi mum, mean, and standard deviation of device parametrics should be evaluated.
Many large OEMs (such as Nortel and Lucent, to name two) are allowing some of their top suppliers to self-qualify by filling out a pre-established template at testing to the fact that various tests and analyses were conducted and that a robust quality infrastructure is in place and functioning. Appropriate documentation is referenced and available to the OEM on demand. Appendix B of Section 4 is an example of a form used by Nortel Networks for self-qualification of programmable logic ICs.
4. Special studies. Special studies are performed for application-specific requirements that the supplier does not specify but are key to successful operation in an application. They include SPICE modeling of I/O to determine signal quality under different loading conditions and varying trace lengths. Special studies provide two benefits:
1. The information gathered allows effective design using a supplier's components.
2. The designer can evaluate second source components for the same application as the primary source.
Non-specified parameter studies/tests should be performed to determine the effects on design requirements. Examples of some non-specified parameters that are critical to digital designs are as follows:
Hot-plot characteristics define the behavior of a device during live insertion/withdrawal applications.
Bus-hold maximum current is rarely specified. The maximum bus-hold cur rent defines the highest value of pull-up/pull down resistors for a design.
It is important to understand transition thresholds, especially when interfacing with different voltage devices. Designers assume 1.5-V transition levels, but the actual range (i.e., 1.3-1.7 V) is useful for signal quality analysis.
Simultaneous switching effect characterization data with 1, 8, and 16 or more outputs switching at the same time allow a designer to manage signal quality as well as current surges in the design.
Pin-to-pin skew defines the variance in simultaneously launched output signals from package extremes.
Group launch delay is the additional propagation delay associated with simultaneous switching of multiple outputs.
5. Package qualification. Component packaging constitutes a technology that often requires special attention to assure a good design fit. Some package characteristics for evaluation are Thermal characteristics in still air and with various air flow rates.
Package parasitics (i.e., resistance, capacitance, and inductance) vary with package type and style. Some packages have more desirable characteristics for some designs.
Manufacturing factors such as solderability, handling requirements, mechanical fatigue, etc.
Advanced packaging innovations such as 3D packages are being used to provide increased volumetric density solutions through vertical stacking of die.
Vertical stacking provides higher levels of silicon efficiency than those achievable through conventional multichip or wafer-level packaging (WLP) technologies.
Through 3D packaging innovations, a product designer can realize a 30 to 50% PWA area reduction versus bare die or WLP solutions. Stacked chip-scale packaging (CSP) enables both a reduction in wiring density required in the PWA and a significant reduction in PWA area. A 60% reduction in area and weight are possible by migrating from two separate thin small outline package (TSOPs) to a stacked CSP. Nowhere is this more important than in the mobile communications industry where aggressive innovations in packaging (smaller products) are required. Examples of several stacked die chip scale packages are shown in Figure 12.
FIGURE 12 Several stacked die CSPs. (Courtesy of Chip Scale Review.)
As the packaging industry migrates to increased miniaturization by employing higher levels of integration, such as stacked die, reliability issues must be recognized at the product development stage. Robust design, appropriate materials, optimized assembly, and efficient accelerated test methods will ensure that reliable products are built. The functionality and portability demands for mobile electronics require extensive use of chip scale packaging in their design. From a field use (reliability) perspective portable electronics are much more subject to bend, torque, and mechanical drops than other electronic products used in business and laboratory environments. As a result traditional reliability thinking, which focuses on having electronic assemblies meet certain thermal cycling reliability requirements, has changed. There is real concern that these products may not meet the mechanical reliability requirements of the application. For stacked packages the combined effects of the coefficient of thermal expansion (CTE ) and elastic modulus determine performance. In stacked packages there is a greater CTE mismatch between the laminate and the package. The failure mechanism may shift to IC damage (cracked die, for example) instead of solder joint damage.
Failures occur along the intermetallic boundaries. Drop dependent failures depend on the nature of the intermetallics that constitute the metallurgical bond.
During thermal cycling, alternating compressive and tensile stresses are operative. Complex structural changes in solder joints, such as intermetallic growths, grain structure modifications (such as grain coarsening and elastic and plastic deformations due to creep) are operative. The different CTE values of the die that make up the stacked package could lead to the development of both delamination and thermal issues. The surface finish of the PWA also plays a significant role in the reliability of the PWA.
Thus, new package types, such as stacked packages, provide a greater challenge for both the IC supplier and the OEM user in qualifying them for use.
6. Functional application testing. Functional application testing (FAT) is the most effective part of component qualification, since it is in essence proof of the design adequacy. It validates that the component and the product design work together by verifying the timing accuracy and margins; testing for possible interactions between the design and components and between hardware, software, and microcode; and testing for operation over temperature and voltage extremes.
The following are examples of functional requirements that are critical to designs and usually are not tested by the component supplier:
Determinism is the characteristic of being predictable. Complex components such as microprocessors, ASICs, FPGAs, and multichip modules should provide the same output in the same cycle time for the same instructions consistently.
Mixed voltage applications, i.e., interfacing devices that operate at different voltages.
Low-frequency noise effects should be assessed for designs that contain devices with phase-locked loops (PLLs). Phase-locked loops are susceptible to low-frequency noise, which could cause intermittent problems.
Hot-plug effects on the system that a module is being hot-plugged into.
Hot-plugging may cause intermittent functional problems.
Figure 13 is a fishbone diagram listing the various items involved in application based qualification. Manufacturers of consumer products with short design and manufacturing life (30-90 days), and short product cycles (6-12 months) require a fast time-to-market mindset. They cannot afford the time necessary to conduct any but the most essential testing. As a result some manufacturers of consumer products are implementing a radical concept: forget about conducting any formal qualification testing and go straight to functional application testing. In fact, they're going one step beyond and letting FAT decide what components and suppliers are right for the application. Thus, in a nutshell, FAT becomes the entire component/supplier selection and qualification process.
FIGURE 13 Example of application-based qualification process flow.
Customer and Supplier Partnership in Application-Based Qualification
Here is that phrase again: customer and supplier partnerships. These relationships are necessary to develop timely and effective qualification of state-of-the-art components and the products that use them. Two specific points are made here.
1. Sharing information is critical to the use of new devices. Suppliers and customers need to identify their needs and explain the rationale for specified requirements. This interchange of information allows both parties to benefit from the experience and knowledge base of the other to create a product that meets the needs of the customer and the sup plier.
2. Product co-development will become more common in the new millennium as custom and semicustom devices become easier to create. Sup pliers and customers will jointly develop new devices to meet specific needs.
Benefits of Application-Based Qualification
1. Lower cost component qualification is a benefit of application-based qualification versus traditional component qualification. Once a technology (wafer process and package type) and/or part family is qualified for a given application there is no need to perform device-by-device qualifications of products from the same family. Only FAT is required. The end result of the application-based qualification is reduced component qualification cycle times.
2. Higher quality products are expected in the new millennium and to achieve product quality improvements there is a need to address an increasing number of no-defect-found industry problems. Application-based qualification uses component application studies to verify that a device is a good fit for a design, placing a greater emphasis on learning about device capability versus testing it to a data sheet. Better understanding of device capability and characteristics enhance a designer's ability to develop a robust design.
3. And, finally, application-based qualification is a process that can grow with changing requirements and technology. The specific attributes evaluated may change with time, but the method and objective of understanding and assessing device capability remains the constant objective.
7.5 Developing A Component Qualification Strategy
Now that I have talked about the past, present and future as regards component qualification, I want to list some of the items that must be considered in developing a component qualification strategy: a standard methodology or thought process that one uses to develop the qualification requirements for a specific application. Every company (OEM) needs to develop a component qualification strategy (typically for their critical components) that is appropriate for the product it makes and the end markets it serves.
Developing a component qualification test strategy involves using the engineering decision-making process in a logical step-by-step situation analysis and applying it to the die, package, technology, and application under consideration. It involves gathering all available data: market trends, technology trends, packaging trends, fab and assembly process data, what has and what hasn't worked in the past and why. It involves an intimate knowledge of both the component and the application, thus necessitating a close working relationship between supplier and OEM and a division of responsibilities. A qualification strategy addresses the application-specific tradeoffs between IC performance, reliability, risk, product performance, and cost and has the following attributes.
It is based on an understanding of the technology and business trends de tailed earlier.
It is a multistep process that begins early in both the component and system design cycles while the designs are in the embryonic stages. From a system perspective it involves the appropriate technology, part, package, and supplier selection.
It is a simple, standard, yet flexible, methodology based on all available data sources-not necessarily a battery of standard tests.
It is concurrent with other engineering activities, not a pass/fail gate.
It is best managed through adherence to a rigorous set of design rules, design reviews, and process controls.
It is based on a detailed understanding of the IC design, physical layout, materials used, material interfaces, packaging details, and potential failure mechanisms (physics of failure concept) to which the device is sensitive by virtue of its wafer fab and assembly processes.
It is application dependent rather than being a standard test or series of tests.
It is easily portable across processes and designs, not requiring re-initialization or even use of all steps taken to date. The caveat here is that the strategy may not be easily ported from one IC technology node to the next (e.g., 0.07-µm technology versus 0.15-µm technology).
It is fast, accurate, and low in cost, not requiring months and tens of thou sands of dollars or more in the design process.
It is specific-component independent, but technology dependent, allowing the rapid qualification of many device types of a given technology.
It is based on a real understanding of reliability
Reliability rules are best verified through design simulations using accurate design-to-process models rather than by life testing an IC.
Reliability issues are an attribute of both the wafer fab processes and the application (e.g., logic states that cause floating buses) and should be addressed through process management techniques (in line process monitors of critical parameters and defect control). Life tests should be performed to characterize the time dependency of reliability defects, an attribute of the process, not specific ICs.
Reliability phenomena need to be checked and verified throughout the design cycle. 70-80% of the operation and maintenance costs are due to choices made in design.
Formal reliability verification must be defined at a higher level and then performed at every level of the design hierarchy, starting at the transistor level and working through to the full chip (IC).
The reality of component qualification is that it is a constantly evolving process, requiring faster throughput and lower cost. Each component (die, pack age, and IC) must be qualified individually by the supplier and then in the product application by the OEM. Each of these requires a complex subset of various evaluations, tests, and analyses. Beyond the year 2000, as the rate of change is accelerating we need to adopt new methods for meeting our overall objectives-fielding reliable products. This means the issue of component qualification needs to be approached with a mind open to all possibilities in meeting end customer needs.
ACKNOWLEDGMENTS
Portions of Sections 3.2 and 3.4 excerpted by permission from the short course "Supplier Management" at the courtesy of Ken Stork and Associates, Inc.
California Institute of Technology. Portions of Section 4 were excerpted from Ref. 3. Portions of Section 6.1 were excerpted from Ref. 4. Sections 7.3 and 7.4 excerpted from Ref. 5.
REFERENCES
1. Moore GA. Living on the Fault Line, Harper Business, 2000.
2. Hnatek ER. Integrated Circuit Quality and Reliability, 2nd ed., Marcel Dekker, 1995.
3. Hnatek ER, Russeau JB. Component engineering: the new paradigm. Advanced Electronic Acquisition, Qualification and Reliability Workshop, August 21-23, 1996, pp 297-308.
4. Hnatek ER, Kyser EL. Practical lessons learned from overstress testing: a historical perspective. EEP Vol. 26-2, Advances in Electronic Packaging, ASME, 1999.
5. Russeau JB, Hnatek ER. Technology qualification versus part qualification beyond the year 2001. Military/Aerospace COTS Conference Proceedings, Berkeley, CA, August 25-27, 1999.
FURTHER READING
1. Carbone J. HP buyers get hands on design. Purchasing, July 19, 2001.
2. Carbone J. Strategic purchasing cuts costs 25% at Siemens. Purchasing, September 20, 2001.
3. Greico PL, Gozzo MW. Supplier Certification II, Handbook for Achieving Excellence Through Continuous Improvement. PT Publications Inc., 1992.
4. Kuglin FA. Customer-centered supply chain management. AMACOM, 1998.
5. Morgan JP, Momczka RM. Strategic Supply Chain Management. Cahners, 2001.
6. Poirier CC. Advanced Supply Chain Management. Berrett-Koehler, San Francisco, CA, 1999.
7. Supply Chain Management Review magazine, Cahners business information publication.
APPENDIX A: SUPPLIER SCORECARD PROCESS OVERVIEW
A.1 Introduction to Scorecard Process What Is a Supplier Scorecard?
A quick and practical approximation of total cost of ownership (TCOO) by measuring major business and performance parameters.
A measure of supplier performance, not just cost.
An evaluation of a supplier's competitiveness (shown by trend analysis).
Why Is a Supplier Scorecard Needed? Gives suppliers status on performance issues and accomplishments.
Provides a clear set of actions needed for continuous improvement, i.e., it sets the baseline.
Provides a regularly scheduled forum between supplier's and customer's top management to discuss overall business relationships and future strategies for moving forward.
Example of the Scorecard Process Top 40 Suppliers
Quarterly process: management reviews for top six to eight suppliers
Scoring methodology:
Who Generates the Score?
----------
Attribute -- Responsibility
Quality Supplier Quality Engineering and Component Engineering OTD Purchasing at both OEM and EMS providers Price OEM commodity manager and Purchasing and EMS Purchasing Support OEM commodity manager and Purchasing and EMS Purchasing Technology Product Design Engineering and Component Engineering
------- General Guidelines
OEM purchasing:
Maintains all historical files and data Issues blank scorecards to appropriate parties Coordinates roll-up scores and emailing of scorecards Publishes management summaries (trends/overview reports) If a supplier provides multiple commodities, then each commodity manager prepares a scorecard and a prorated corporate scoreboard is generated.
Each commodity manager can then show a supplier two cards--a divisional and an overall corporate scorecard.
The same process will be applied (prorated by dollars spent) for an OEM buyer and a EMS buyer.
Scorecard Process Timetable Example
Week one of quarter: gather data.
Week two of quarter: roll-up scorecard and review results.
Goal: scorecards will be emailed to suppliers by the 15th of the first month of the quarter.
Executive meetings will be scheduled over the quarter.
A.2 Scorecard Metrics
Product and process quality might be worth up to 20 points, for example. Points are deducted for each quality problem resulting in the supplier's product being returned for rework or requiring rework by the OEM in order to be usable in the OEM's product. The number of points deducted is determined by the supplier quality engineer based on the severity and impact of the problem, and by the age of the items involved:
Catastrophic Minus 20 points
Serious Minus 5 points Minor Minus 1 point
Management system quality might be rated for up to 5 points, as follows:
1 point for an internal continuous process improvement program with defined goals and documented improvement plans that are shared with the OEM on a quarterly basis.
1 point for improved first pass yield and/or other key quality indicator reports that are provided to the OEM monthly.
1 point for no open supplier corrective action requests older than 30 calendar days.
1 point for documented quality requirements imposed upon supplier's purchased material; monitored material quality reports provided to the OEM.
1 point if the supplier is certified to ISO 9000.
On-time delivery points might be allocated as follows:
Requested due date is usually the suggested due date.
Original due date is the supplier's original commit date.
Latest due date is the supplier's latest commit date.
Supplier performance: 5 days early/0 days late (measured as difference between the OEM receipt date and original due date).
Supplier flexibility: 5 days early/0 days late (measured as difference be tween receipt date and requested due date).
APPENDIX B: SELF-QUALIFICATION FORM FOR PROGRAMMABLE LOGIC ICs
The following documentation reproduces the self-qualification form for programmable Logic ICs used by Nortel Networks Inc.